R.E. Bryant, S. German, , and M.N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):93--134, January 2001. Home/Search Document Not in Database Summary Related Articles Check |
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Two Solutions to Incorporate Zero, Successor and Equality in.. - Badban, Pol (Correct)
....propositional variables. The resulting formula can be checked for satisfiability with any existing SAT technique, for instance based on resolution or on BDDs. An early example is Ackermann s reduction [1] by which second order variables can be eliminated. More optimal versions can be found in [15, 20, 11]. Recently, this method is applied in [24] to boolean combinations over successor, predecessor, equality and inequality over the integers, in [28] it is applied to separation predicates x y c, and in [27] Pressburger arithmetic for integers, and linear arithmetic for reals are translated into ....
....relevance of separation formulas of the form x y c. A similar fragment is also used in real time model checking as in Uppaal [6, 5] Propositional logic with equality and uninterpreted functions (EUF) has been proposed for verifying correctness of hardware designs [12] Also the techniques of [11] are applied to proving equivalence of hardware designs. In [20] similar techniques are applied to the verification of the correctness of compiler optimization results. Finally, these kind of decision procedures are built into many modern interactive theorem provers, such as PVS [19] and SVC [4] ....
R.E. Bryant, S. German, and M.N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACMTCL: ACM Transactions on Computational Logic, 2, 2001.
Two Solutions to Incorporate Zero, Successor and Equality in.. - Badban, Pol (2002) (Correct)
....propositional variables. The resulting formula can be checked for satisfiability with any existing SAT technique, for instance based on resolution or on BDDs. An early example is Ackermann s reduction [1] by which second order variables can be eliminated. More optimal versions can be found in [15, 20, 11]. Recently, this method is applied in [24] to boolean combinations over successor, predecessor, equality and inequality over the integers, in [28] it is applied to separation predicates x y c, and in [27] Pressburger arithmetic for integers, and linear arithmetic for reals are translated into ....
....relevance of separation formulas of the form x y c. A similar fragment is also used in real time model checking as in Uppaal [6, 5] Propositional logic with equality and uninterpreted functions (EUF) has been proposed for verifying correctness of hardware designs [12] Also the techniques of [11] are applied to proving equivalence of hardware designs. In [20] similar techniques are applied to the verification of the correctness of compiler optimization results. Finally, these kind of decision procedures are built into many modern interactive theorem provers, such as PVS [19] and SVC ....
R.E. Bryant, S. German, and M.N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACMTCL: ACM Transactions on Computational Logic, 2, 2001.
Convergence Testing in Term-Level Bounded Model Checking - Bryant, Lahiri, Seshia (2003) Self-citation (Bryant) (Correct)
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R. E. Bryant, S. German, and M. N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):1--41, January 2001.
Convergence Testing in Term-Level Bounded Model Checking - Bryant, Lahiri, Seshia (2003) Self-citation (Bryant) (Correct)
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R. E. Bryant, S. German, and M. N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):1--41, January 2001.
Transforming Equality Logic to Propositional Logic - Zantema, Groote (Correct)
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R.E. Bryant, S. German, , and M.N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):93--134, January 2001.
DPLL(T): Fast Decision Procedures - Ganzinger, Hagen, Nieuwenhuis.. (2004) (1 citation) (Correct)
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R. E. Bryant, S. German, and M. N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Trans. Computational Logic, 2(1):93--134, 2001.
The UCLID Decision Procedure - Lahiri, Seshia (2004) (1 citation) (Correct)
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R. E. Bryant, S. German, and M. N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Transactions on Computational Logic, 2(1):1--41, January 2001.
DPLL(T): Fast Decision Procedures - Ganzinger, Hagen, Nieuwenhuis.. (2004) (1 citation) (Correct)
No context found.
R. E. Bryant, S. German, and M. N. Velev. Processor verification using e#cient reductions of the logic of uninterpreted functions to propositional logic. ACM Trans. Computational Logic, 2(1):93--134, 2001.
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