| Jullien, G.A., Miller, W.C., Grondin, R., Wang, Z., Zhang, D., Del Pup, L., and Bizzan, S. "Woodchuck: A Low-Level Synthesizer for Dynamic Pipelined DSP Arithmetic Logic Blocks." Proceedings of the International Symposium on Circuits and Systems, 1, pp.176-179, 1992. |
....the delay terms through the effective resistance of each transistor. The authors proposed an analytical approach to the FET chain tapering problem based on an observation that the delay terms were equal in near optimally sized FET chains. This has been incorporated into an automated layout system [8]. However, they could not give any analytical proof for their observation. In this paper, we propose a new tapering shape which is a composition of constant and exponential functions. We give analytical proof that the proposed tapering scheme is optimal in the long chain limit. Simulations ....
G. A. Jullien, W. C. Miller, R. Grondin, Z. Wang, L. Del Pup, and B. Bizzan, "Woodchuck: A Low-Level Synthesizer for Dynamic Pipelined DSP Arithmetic Logic Blocks," Proc. IEEE Int. Symp. on Circuits and Systems, pp. 176-179, 1992.
No context found.
Jullien, G.A., Miller, W.C., Grondin, R., Wang, Z., Zhang, D., Del Pup, L., and Bizzan, S. "Woodchuck: A Low-Level Synthesizer for Dynamic Pipelined DSP Arithmetic Logic Blocks." Proceedings of the International Symposium on Circuits and Systems, 1, pp.176-179, 1992.
No context found.
Jullien, G.A., Miller, W.C., Grondin, R., Wang, Z., Zhang, D., Del Pup, L., and Bizzan, S., 1992. "WoodChuck: A Low-Level Synthesizer for Dynamic Pipelined DSP Arithmetic Logic Blocks." 1992 IEEE Int. Symp. on Circuits and Systems, San Diego, pp. 176-179
No context found.
Jullien, G. A., W. C. Miller, R. Grondin, Z. Wang, D. Zhang, L. D. Pup and S. Bizzan. "WoodChuck: A Low-Level Synthesizer for Dynamic Pipelined DSP Arithmetic Logic Blocks." IEEE International Symposium on Circuits and Systems. vol. 1 pp. 176-179, 1992.
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