| P. Faraboschi, F. Homewood, ST200: A VLIW Architecture for Media-Oriented Applications, Microprocessor Forum 2000. |
....with a 5 stage pipeline that executes most basic instructions in one clock cycle. The SH3 implements a 16 bit ISA but fetches two instructions in a single access. The target processor is the Lx ST210 4 wide VLIW embedded core jointly developed by Hewlett Packard and STMicroelectronics [13][14]. The system (Figure 3) comprises a traditional interpreted emulator for an SH3 ISA, complemented by enough system components (timers, serial ports, display, etc. to be able to support a (simple) configuration of the WinCE kernel, after we wrote a hardware abstraction layer for it. The other ....
P. Faraboschi, F. Homewood, ST200: A VLIW Architecture for Media-Oriented Applications, Microprocessor Forum 2000.
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