R. Espasa et al. Tarantula: a vector extension to the Alpha architecture. In ISCA-29, 2002. Home/Search Document Not in Database Summary Related Articles Check |
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Vector vs. Superscalar and VLIW Architectures for Embedded .. - Kozyrakis, Patterson (2002) (1 citation) (Correct)
....SIMD arithmetic and complicates automatic compilation. The majority of recent work in vector architectures has focused on adopting techniques from superscalar designs (decoupling [9] out of order execution [11] simultaneous multithreading [10] in order to accelerate scientific applications. In [8], Espasa showed that Tarantula, an 8 lane vector extension to the EV8 Alpha processor, achieves a 5x speedup over a dual processor EV8 chip of similar complexity and power consumption. Nevertheless, a few academic groups have studied vector designs with multimedia. T0, a SRAM based vector ....
R. Espasa, J. Emer, et al. Tarantula: a Vector Extension to the Alpha Architecture. In the Proceedings of the 29th Intl. Symposium on Computer Architecture, Anchorage, AL, May 2002.
Overcoming the Limitations of Conventional Vector Processors - Kozyrakis, Patterson (2003) (9 citations) (Correct)
.... architectures offer significant advantages over superscalar processors for a wide range of compute intensive applications: multimedia (VIRAM [19] Imagine [15] broadband and wireless communication (Intel IXS [26] Broadcom Calisto [20] bioinformatics workloads (Cray X1 [1] Tarantula [7]) climate modeling (NEC ES [24] The abundance of data level parallelism in such tasks allows them to concurrently execute tens of arithmetic and memory operations, while issuing a single instruction per cycle [6] For data parallel tasks, vector processors approach the performance and power ....
....cost. 3 The CODE Microarchitecture This section introduces CODE (Clustered Organization for Decoupled Execution) within the context of the VIRAM ISA for multimedia processing. However, CODE is equally applicable to any other modern vector ISA, such as the Cray X1 [1] or the Alpha Tarantula [7]. A complete description of CODE is available in [18] The VIRAM ISA is a vector load store extension to the MIPS architecture. It defines a 8 KByte vector register file that stores 32 general purpose registers with 32 64 bit, 64 32 bit, or 128 16 bit elements per register. Integer, ....
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R. Espasa et al. Tarantula: a Vector Extension to the Alpha Architecture. In the Proceedings of the 29th Intl. Symp. on Computer Architecture, pages 281--291, Anchorage, AL, May 2002.
Exploiting ILP, TLP, and DLP with the Polymorphous .. - Sankaralingam.. (2003) (3 citations) (Correct)
....at processor design time. One strategy for combating processor fragility is to build a heterogeneous chip, which contains multiple processing cores, each designed to run a distinct class of workloads effectively. The proposed Tarantula processor is one such example of integrated heterogeneity [8]. The two major downsides to this approach are (1) increased hardware complexity since there is little design reuse between the two types of processors and (2) poor resource utilization when the application mix contains a balance different than that ideally suited to the underlying heterogeneous ....
....a factor of 2.4 higher than the D morph. A more idealized S morph configuration that employs 256 frames and no revitalization latency improves performance to 9 compute ops cycle, 26 higher than the realistic S morph. An alternative approach to S morph polymorphism is the Tarantula architecture [8] which exploits data level parallelism by augmenting the processor core of an Alpha 21464 with a dedicated vector data path of 32 ALUs, an approach that sustains between 10 and 20 FLOPS per cycle. Our results indicate that the TRIPS S morph can provide competitive performance on data parallel ....
R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proceedings of The 29th International Symposium on Computer Architecture, pages 281--292, May 2002.
Cache Refill/Access Decoupling for Vector Machines - Batten, Krashinsky.. (2004) (Correct)
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R. Espasa et al. Tarantula: a vector extension to the Alpha architecture. In ISCA-29, 2002.
Universal Mechanisms for Data-Parallel Architectures - Sankaralingam, Keckler.. (Correct)
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R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proc. of the 29th Int'l Symp. on Computer Architecture, pages 281--292, June 2002.
Universal Mechanisms for Data-Parallel Architectures - Sankaralingam, Keckler.. (2003) (1 citation) (Correct)
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R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proc. of the 29th Int'l Symp. on Computer Architecture, pages 281--292, June 2002.
Universal Mechanisms for Data-Parallel Architectures - Sankaralingam, Keckler.. (Correct)
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R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec. Tarantula: A Vector Extension to the Alpha Architecture. In Proc. of the 29th Int'l Symp. on Computer Architecture, pages 281--292, June 2002.
Evaluation of the Raw Microprocessor: An.. - Taylor, Lee.. (2004) (6 citations) (Correct)
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R. Espasa, et al. Tarantula: A Vector Extension to the Alpha Architecture. 2002 ISCA, pp. 281--292.
Single-ISA Heterogeneous Multi-Core Architectures.. - Kumar, Tullsen.. (2004) (1 citation) (Correct)
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R. Espasa, F. Ardanaz, J. Emer, S. Felix, J. Gago, R. Gramunt, I. Hernandez, T. Juan, G. Lowney, M. Mattina, and A. Seznec. Tarantula: A vector extension to the alpha architecture. In International Symposium on Computer Architecture, May 2002.
Stream Register Files with Indexed Access - Nuwan Jayasena Mattan (2004) (2 citations) (Correct)
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R. Espasa, F. Ardanaz et. al. Tarantula: A Vector Extension to the Alpha Architecture. In Proc. of the 29 Intl. Symposium on Computer Architecture, pp. 281-292, May. 2002.
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