D. Panigrahi, C. N. Taylor, and S. Dey, "Interface based hardware/software validation of a system-on-chip", in High Level Design Validation and Test Workshop, pp. 53--58, 2000. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Hardware-Software Covalidation: Fault Models and Test Generation - Harris (Correct)
....design methodologies which utilize pre designed, pre verified cores. Since each core component is pre verified, the system covalidation problem focuses on the interface between the components. A case study of the interface based covalidation of an image compression system has been presented [49]. Researchers classify the interface fault which occurred during the design process into three groups: 1) COMP2COMP faults involving communication between pairs of components, 2) COMP2COMM faults involving the interaction between each component and the communication architecture, and 3) COMM ....
....faults involving communication between pairs of components, 2) COMP2COMM faults involving the interaction between each component and the communication architecture, and 3) COMM faults involving the coordinated interactions between the communication architecture and all components. In [49], test benches are developed manually to target each of these interface fault classes. Additional interface complexity is introduced by the use of multiple clock domains in large systems. The interfaces between different clock domains must be essentially asynchronous, making them particularly ....
D. Panigrahi, C. N. Taylor, and S. Dey, "Interface based hardware/software validation of a system-on-chip", in High Level Design Validation and Test Workshop, pp. 53--58, 2000.
Verification of a complex SoC; the PRO³ case-study - Andritsopoulos.. (Correct)
....files, that presented all the transactions in a readable format, accelerating the debug process of each block. After the verification of each individual block, the next step was the hierarchical integration of the neighboring blocks and the verification of interfaces and interconnect architecture [10]. When this task was successfully finalized, the designers started the system level verification of PRO , which was partitioned to separate groups, each one responsible to run end to end scenarios for the demonstration applications. In order to test the PRO chip it is necessary to configure ....
D. Panigrahi, C. Taylor, and S. Dey. Interface based hardware /software validation of a system-on-chip. IEEE International High Level Design Validation and Test Workshop (HLDVT), 2000.
A Hardware/Software Reconfigurable Architecture for.. - Panigrahi, Taylor, Dey (2002) (1 citation) Self-citation (Panigrahi Taylor Dey) (Correct)
No context found.
D. Panigrahi, C. N. Taylor, and S. Dey. Interface based hardware /software validation of a system-on-chip. In Proceedings of 5th IEEE HLDVT Workshop, November 2000.
Fault Models and Test Generation for Hardware-Software.. - Ian Harris Department (Correct)
No context found.
D. Panigrahi, C. N. Taylor, and S. Dey, "Interface based hardware/software validation of a system-on-chip", in High Level Design Validation and Test Workshop, pp. 53--58, 2000.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC