| R. Maestre, F. Kurdahl, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A formal approach to context scheduling for multicontext reconfigurable architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1) (2001) 173--185. |
....a regular structure or being distributed along the computational resources to act as a local distributed register file. We furthermore assume that architectural assists are available to tackle the reconfiguration penalty problem (i.e. multicontext configuration memory, configuration cache [12] 14][15]) 3. Methodology and Programming Model We compile the whole application using the ST200 compiler (based on Multiflow[8] and profile the performances on the ST200 compiled simulator, which also embeds I and D cache models. An inspection of the code representing the bottlenecks then drives the ....
....We assume the RFU to have no reconfiguration penalty. This gives an upper bound performance assessment, which should be approached in real cases, by developing smart reconfiguration strategies, based on configuration prefetch and management, to hide the reconfiguration penalties [12] 14][15]. We furthermore assume to generate RFU instruction configurations which fit the RFU size and available resources. The preliminary way we propose to use the reconfigurable unit resembles the methodology for embedded systems, where the requirements usually force the designer to adopt mixed ....
R. Maestre et al. "A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures," IEEE Trans. on VLSI Systems, Vol.9, no.1, Feb.2001, pp.173-185.
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R. Maestre, F. Kurdahl, M. Fernandez, R. Hermida, N. Bagherzadeh, H. Singh, A formal approach to context scheduling for multicontext reconfigurable architectures, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 9 (1) (2001) 173--185.
No context found.
Maestre, R., Kurdahi, F. J., Hermida, R., Bagherzadeh, N., Singh, H., A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures. IEEE Transactions on Very Large Scale Integration Systems, Vol. 9, No. 1, February 2001, pp. 173-185.
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