A.Marshall, B. Coates and Polly Siegel, \Designing an Asynchronous Communications Chip", IEEE Design & Test of Computers vol. 11, no. 2, pp. 8-21, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....a benchmark that has never been possible to solve exactly in number of literals before. 1 Introduction In recent years, there has been a number of successful and practical asynchronous circuits designed using asynchronous finite state machines in the form of extended burstmode controllers [3, 19, 15, 23, 7]. During the design process, it is necessary to try different protocols and state assignments to find a good circuit implementation. This often leads to many iterations through the synthesis process. The bottleneck of finite state machine synthesis is typically in the two level hazard free logic ....

A. Marshall, B. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8--21, 1994.

.... tool described in this paper was used to design significant portion of control circuitry for Intel s Asynchronous Instruction Length Decoder chip, a high performance differential equation solver chip [27] a high performance SCSI controller [28] and a low power infrared communication chip [29]. All the 3D controllers in the fabricated chips worked correctly in first silicon. This paper is divided into two parts: part I describes the specification formalism and the hazard free implementations and part II presents automatic synthesis and experimental results. Section II of Part I ....

A. Marshall, B. Coates, and P. Siegel, "Designing an asynchronous communications chip," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 8--21, 1994.

....6 2 micron or 0.5 micron process, at a temperature of 30 ffi C or immersed in liquid nitrogen, and at varying voltages. Modifying these parameters can effect the power consumption and performance dramatically. 6. The interfaces can be extremely robust, including the adaption to timed protocols [MCS94] 7. Fewer constraints may be required regarding the physical placement and routing of cells, simplifying implementation details. 8. Observability may be easier to achieve using the stuck at fault model because a handshake signal that cannot make a transition results in deadlock. While faults ....

....these arrivals would have to be normalized to the system clock, resulting in slower delivery. Receptive asynchronous systems begin processing packets as soon as data arrives [NDDH93] This robustness of interfaces is also being investigated for commercial applications in noisy environments [MCS94] The low power nature of asynchronous architectures was one further advantage demonstrated in the Post Office. Asynchronous circuits contain fine grain, dynamic power management due to the handshake protocols. Each idle Mayfly PE requires 30 amperes of current at 5 volts. By way of contrast, ....

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Alan Marshall, Bill Coates, and Polly Siegel. Designing an Asynchronous Communications Chip. IEEE Design & Test of Computers, 11(2):8--21, summer 1994. CHAPTER 8. BIBLIOGRAPHY 229

....algorithms that share resources over subsequent computation steps. synchronous (product) version. The single rail was clearly superior and consumed five times less power than the synchronous version. A second example is the infrared communications receiver IC designed at Hewlett Packard Stanford [30]. The receiver IC draws only leakage current while waiting for incoming data, but can start up as soon as a signal arrives so that it loses no data. Also, most modules operate well below the maximum frequency of operation. The filter bank for a digital hearing aid was the subject of another ....

Alan Marshall, Bill Coates, and Polly Siegel, "Designing an asynchronous communications chip," IEEE Design & Test of Computers, vol. 11, no. 2, pp. 8--21, 1994.

....sufficiently general to describe practical circuits. 1. Introduction There has been a renewed interest in asynchronous circuits in recent years due to their advantages over synchronous circuits in performance and power consumption and as a way to eliminate problems related to clock skew [3, 5, 9, 16, 17]. However many of these advantages are often reduced or eliminated completely when the additional overhead in both speed and area that is required to build correct asynchronous circuits is included. This overhead mostly derives from the necessity to design a circuit that works correctly while ....

A. Marshall, B. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8--21, 1994.

....sending of another byte, while the second, to state 6 represents the signaling of the end of transmission. Using this design style, SCSI interfaces, cache controllers, an infrared communications controller, as well as a variety of interface specifications have been designed with promising results [9, 12, 17, 16, 18, 7]. This paper provides efficient algorithms for quantifying the energy consumption of burst mode circuits implemented with twolevel or multi level logic. Since different modes of circuit operation mayconsume different amounts of energy, we must determine the relative likelihood of executing ....

A. Marshall, B. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8-- 21, 1994.

....Second, asynchronous circuits have an inherent automatic power down operation: modules are activated only when their operations are needed. Low power operation is a major focus of recent asynchronous design, including large scale, fabricated examples like a low power infrared communications chip [9], an asynchronous implementation of the ARM microprocessor [6] and an asynchronous error corrector for a DCC player [24] A number of asynchronous design methods have been introduced recently [21, 10, 2, 16, 28, 15, 25] Several methods build asynchronous circuits as networks of communicating ....

A. Marshall, B. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8--21, Summer 1994.

....encoding is more flexible in the implementations. Burst mode specifications have been very useful in specifying large, practical controllers, such as a SCSI data transfer protocol controller [54] an asynchronous high performance cache controller [51] and asynchronous communications controllers [37]. Its main practical disadvantage is that it does not allow input changes to be concurrent with output changes. The input choice mechanism is more flexible than the STG but still primitive. For example, it cannot handle choices between two sets of concurrent events if one set is a subset of the ....

A. Marshall, W. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, pages 8--21, Summer 1994.

....circuits and reduces run times by over an order of magnitude. The block level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate level speed independent circuits. 1 Introduction As competitive asynchronous chips gain attention [9, 14, 20, 34, 44, 49, 51], asynchronous design is increasingly being considered as a practical and efficient design alternative. Asynchronous designs do not require a global clock for synchronization. Instead, synchronization is event driven in that transitions on wires act to request the start of a computation and ....

A. Marshall, B. Coates, and P. Siegel. Designing an asynchronous communications chip. IEEE Design & Test of Computers, 11(2):8--21, 1994.

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A.Marshall, B. Coates and Polly Siegel, \Designing an Asynchronous Communications Chip", IEEE Design & Test of Computers vol. 11, no. 2, pp. 8-21, 1994.

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A. Marshall, B. Coates, P. Siegel, "Designing an asynchronous communications chip," IEEE Design and Test of Computers, vol. 11, pp. 8-21, Summer 1994.

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