Ho-Seop Kim and James E. Smith. Dynamic binary translation for accumulator-oriented architectures. In Proceedings of the international symposium on Code generation and optimization, pages 25--35. IEEE Computer Society, 2003. Home/Search Document Details and Download
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....when compared with the conventional scheme. As a result, 7 and 3 IPC improvements are achieved for an 8 way and a 4 way superscalar processors, respectively, while a conventional scheme reports IPC losses of 2.6 and 6.8 . 1. Introduction In a co designed virtual machine (VM) system [1,15,25,27,41], a combination of hardware and software are designed concurrently in order to implement a conventional instruction set architecture (ISA) The software component of the VM dynamically translates from the 2 25 architected ISA to a proprietary, implementation specific ISA that is implemented by the ....
....at all times. In the IBM DAISY system the PowerPC ISA is translated to a proprietary VLIW implementation. The Transmeta Crusoe translates the x86 ISA to proprietary VLIW. Of course, one can also envision systems that translate to ISAs that are targeted at out of order superscalar implementations [25,41]. In these systems, two types of optimizations are going on at once: the most obvious is the dynamic translation from one instruction set to another, but another is the re organization of instruction sequences and caching them in the hidden region of main memory. This process occurs naturally as ....
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Ho-Seop Kim and James E. Smith, "Dynamic Binary Translation for Accumulator-Oriented Architectures," to be published in Proc. 1 Int. Symp. Code Generation and Optimization, 2003.
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Ho-Seop Kim and James E. Smith. Dynamic binary translation for accumulator-oriented architectures. In Proceedings of the international symposium on Code generation and optimization, pages 25--35. IEEE Computer Society, 2003.
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