Nicholas Kohout, Seungryul Choi, Dongkeun Kim, and Donald Yeung. Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointer-chasing codes. In Proceedings of the 10th International Conference on Parallel Architectures and Compilation Techniques, Barcelona, Spain. September 2001. Home/Search Document Details and Download
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Correlation Prefetching with a User-Level Memory Thread - Solihin, Lee, Torrellas (2003) (Correct)
....helper threads, intelligent memory architecture, processing in memory, heterogeneous system. # 1INTRODUCTION D ATA prefetching is a popular technique to tolerate long memory access latencies. Most of the past work on data prefetching has focused on processor side prefetching [6] 7] [8], 15] 16] 17] 18] 23] 24] 28] 30] 32] 35] 36] In this approach, the processor or an engine in its cache hierarchy issues the prefetch requests. An interesting alternative is memory side prefetching, where the engine that prefetches data for the processor is in the main memory ....
....and the Stream buffers of Jouppi [16] Palacharla and Kessler [28] and Sherwood et al. 32] We base our processor side prefetcher on these schemes. There are many more proposals for processor side prefetching, often for irregular applications. A tiny, nonexhaustive list includes Choi et al. [8], Karlsson et al. 17] Lipasti et al. 23] Luk and Mowry [24] Mehrotra [25] Roth et al. 30] and Zhang and Torrellas [36] Many of these schemes specifically target linked data structures. Many of them rely on program information that is available to the processor, like the addresses and ....
S. Choi, D. Kim, and D. Yeung, "Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes," Proc. Int'l Conf. Parallel Architectures and Compilation Techniques, pp. 51-61, Sept. 2001.
Effective Compile-Time Analysis for Data Prefetching in Java - Cahoon (2002) (Correct)
....and a use. 34 The preloading heuristic slightly increases code size and the number of spilled registers, but they show execution time improvements in most of the SPEC92 benchmarks. Kohout, Choi, Kim, and Yeung propose and evaluate a programmable prefetch engine for prefetching linked structures [61]. The technique prefetches a single linked list sequentially, but attempts to prefetch multiple lists simultaneously. For this technique to be effective, the compiler or programmer must identify independent linked structures. The programmable prefetch engines uses the compiler or programmer ....
Nicholas Kohout, Senugryul Choi, Dongkeun Kim, and Donald Yeung. Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointerchaising codes. In Proceedings of the 2001.
Configurable Dynamic Hardware Prefetching Of Linked Data Structures - Wise (2003) (Correct)
....effectively represented by their recurrence model, while WiseNPA s generalized architecture can support LDSs of nearly any complexity. Multichain prefetching is a different approach that takes advantage of cases where multiple independent streams of LDS traversals can be prefetched in parallel [11 ]. This method does provide the prefetch engine with information about the LDS data structure, but in a more limited format than WiseNPA. Also, describing complex data structures requires composing layout descriptors, while WiseNPA supports them naturally in its generalized architecture. The ....
....the prefetch engine with information about the LDS data structure, but in a more limited format than WiseNPA. Also, describing complex data structures requires composing layout descriptors, while WiseNPA supports them naturally in its generalized architecture. The hardware address generator in [11 ] only supports software initiated prefetches, while WiseNPA also supports dynamic hardware initiated prefetches. Also, 11] does not deal with mis speculated traversals of complex LDSs, while WiseNPA does support adaptive dynamic and prediction methods to support this. The previous methods ....
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N. Kohout, S. Choi, K. Dongkeun, and D. Yeung, "Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointer-chasing codes," in Proceedings of the 2001.
Cache-Conscious Allocation of Pointer-Based Data.. - Hallberg, Palm, Brorsson (2003) (Correct)
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Nicholas Kohout, Seungryul Choi, Dongkeun Kim, and Donald Yeung. Multi-chain prefetching: Effective exploitation of inter-chain memory parallelism for pointer-chasing codes. In Proceedings of the 10th International Conference on Parallel Architectures and Compilation Techniques, Barcelona, Spain. September 2001.
Using a User-Level Memory Thread for Correlation Prefetching - Yan Solihin Jaejin (2002) (11 citations) (Correct)
No context found.
S. Choi, D. Kim, and D. Yeung. Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. In International Conference on Parallel Architectures and Compilation Techniques, pages 51--61, September 2001.
Using a User-Level Memory Thread for Correlation Prefetching - Yan Solihin Jaejin (2002) (11 citations) (Correct)
No context found.
S. Choi, D. Kim, and D. Yeung. Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. In International Conference on Parallel Architectures and Compilation Techniques, pages 51--61, September 2001.
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