V. Chaiyakul, D. Gajski, and L. Ramachandran. High-level transformations for minimizing syntactic variances. In Design Automation Conference, June 1993.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....RT gate level. The nodes of the hardware graph represent the inferred functional units and gates that implement the functionality described in the model. The purpose of this step is to produce a design representation that minimizes any bias on the partitioning of the design due to HDL coding style [7]. The hardware graph serves as the input to the partitioning routines that constitute the second phase. The partitioning phase begins by dividing the hardware graph into subgraphs to reduce computational complexity. These subgraphs serve as the leaf nodes clustered using the hierarchical ....

.... RTL Model Hardware Inference Hardware Graph Subgraph Decomposition Hierarchical Clustering Cutline Evaluation Partition Classification Partitioned Design Figure 2 Overview of the partitioning process to a structural representation very similar to the ADD representation [7]. The nodes of the hardware graph are chosen from a technology independent target library consisting of cells derived from the operators in the Verilog language, in addition to other cells like multiplexers and registers that implement functionality inferred from language semantics. The close ....

V. Chaiyakul, et al., "High-Level Transformations for Minimizing Syntactic Variances," in Proceedings of the 30th Design Automation Conference, pp. 413-418, 1993.

....Select direction default direction vertical direction line[n] line[n 1] line[n 1] interpolated current field line[n] line Figure 12. Architecture of a direction detector for IPSC algorithms. process. Examples include [14] which uses a (pseudo) normalization step to dispose of it. In [19] a representation format, targeted at the translation of VHDL, is developed which should be capable of representing all equivalent behaviors in one unique way. Besides the fact that neither systems achieves such a unique representation we believe it is not preferable either. The implementation ....

V. Chaiyakul, D.D. Gajski, L. Ramanchandran, High-Level Transformations for Minimizing Syntactic Variances, Proc. of DAC 93, pp. 413-418, 1993.

....often specified by means of an algorithm in an executable language. These algorithms represent both behavior and structure. This latter is called the initial implementation suggestion. Different algorithms can be used to specify the same behavior, this is known assyntactic variance. Many, such as [CGR93, Jan94], consider this a problem and try to rewrite the syntax to obtain a unique normal form for each behavior. In contrast, we believe that this initial implementation suggestion often contains useful pointers into the design space. Furthermore, preserving the original structure makes the design flow ....

....this representation model is very simple compared to SIL and uses only structural transformations. Furthermore, the proof assumes the existence of a normal form of a behavior and the use of invertible transformations. As far as we know such a normal form is not known and attempts to define one [Jan94, CGR93] have failed. Because transformations on SIL can reduce design freedom (for example, the transformations used for quantization shown in Figure 7) they are not generally invertible. Because of the large number of transformations, the efficiency of the process of implementing and verifying ....

V. Chaiyakul, D.D. Gajski, L. Ramanchandran, High-Level Transformations for Minimizing Syntactic Variances, Proc. of DAC 93, pp. 413-418, 1993.

....are required for preserving the implementation suggestion and are different from most other CDFG languages. 5.2. Implementation Suggestion While others consider the implementation suggestion an unwanted side effect of the specification process requiring a normalization step to dispose [Jan94, CGR93, Gaj94] we do not. On the contrary, the implementation suggestion may very well be intended by the designer and contain valuable pointers in the design space towards the optimal solution. This is especially so if the specification is written by an experienced designer. Furthermore, preserving ....

....purpose of synthesis. Therefore, any approach not capable of representing such an implementation suggestion in an unambiguous way is not suitable as backbone for synthesis. On the other hand, being able to change or remove part of the implementation suggestion is essential. Techniques proposed in [CGR93 and Jan94] are useful for this latter aspect but neither is capable of obtaining a unique, normalized representation for each behavior. Due to the (intentional) ambiguity in the representation of the implementation suggestion in [CGR93] we think the format is not suited as backbone for ....

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V. Chaiyakul, D.D. Gajski, L. Ramanchandran, High-Level Transformations for Minimizing Syntactic Variances, Proc. of DAC 93, pp. 413-418, 1993.

....for design description, several approaches proposed by [4] can identify specific syntactic constructs and replace them with attributes on signals and nets to indicate their functions. Furthermore, in order to reduce the syntactic variation of descriptions with the same semantic, Chaiyakul et al. [8] proposed a transformation technique using an Assignment Decision Diagrams (ADD) to minimize syntactic variance in the description. The graph capturing the behavior can be restructured. Tree height reduction is one of the commonly used flow graph transformations to improve the parallelism of the ....

V. Chaiyakul, D. D. Gajski, and L. Ramachandran, "High Level Transformation for Minimizing Syntactic Variances," Proceedings of the Design Automation Conference (DAC), pp. 413-418, June 1993.

....0.00 Figure 4: Results of building SLIF and obtaining estimations To demonstrate the efficiency of SLIF over other formats, we compared the size of two other formats with that of SLIF for the fuzzy logic controller example. The SLIF AG for the example required 35 nodes and 56 edges. The ADD format [30], which is similar in form and complexity to the VT format, required over 450 nodes and 400 edges. The CDFG format required over 1100 nodes and 900 edges. The difference in complexity greatly affects the types of partitioning algorithms that can be applied. For example, if an n 2 algorithm is to ....

V. Chaiyakul and D. Gajski, "High-level transformations for minimizing syntactic variances," in Proceedings of the Design Automation Conference, 1993.

....system must try to capture the intent of the designer instead of implementing the description in a straight forward manner. To capture the intent is a task which is very difficult. Recently there has been some research on how to minimise the syntactic variances of the synthesis results. In [ChGaRa 93] Chaiakul et al. describe a method to reduce the syntactic variances caused by different styles of writing conditional statements in the behavioural code of the specification. JaCaMa 94] uses a set of 13 simple transformations to optimise the structure of a signal flow graph in order to ....

V. Chaiakul, D.D. Gajski, L. Ramachandran, "High-Level Transformations for Minimizing Syntactic Variances", In Proc. of 30th ACM/IEEE Design Automation Conference, 1993.

....how the synthesis tool interprets the input language and thus must spend a lot of time juggling the synthesis system around instead of spending it on real hardware design. To solve this problem transformations that minimise the syntactic variances in the input descriptions must be applied. In [CGR 93] a method for minimising the syntactic variances in the input description for control structures (IF, WHILE, CASE) is described. Conditional variances have a much larger impact on the final design since these are more dependent on the programming style than any other type of construct. However, ....

Viraphol Chaiyakul, Daniel D. Gajski and Loganath Ramachandran, "High-Level Transformations for Minimizing Syntactic Variances", In Proc. of the 30th Design Automation Conference, pp 413-418, June 1993.

....hardware in a unique, precise, and simple manner. We regard these three objectives with utmost importance because of the following reasons. ffl The uniqueness of the representation will allow synthesis tools to be independent of syntactic variances that are present in the input description. In [5] we have proposed the most parallel representation to be the unique representation. Hence, the ADD has to be able to depict the most parallel representation of a given description in order to satisfy the uniqueness property. ffl In addition to being unique, the representation we are seeking ....

....conditional and assignment statements. A synthesis system that uses the ADD can produce consistent results for descriptions that are differed in such ordering or grouping of statements but are functionally equivalent. Discussion of minimizing syntactic variance scheme is provided in section 5 and [5]. ffl Allocation Since control dependencies are represented as data dependencies, the notion of basic block is absent in the ADD. This means determining allocation for the whole design would require only a simple data flow based allocation algorithm. ffl Scheduling Similar to the ....

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V. Chaiyakul, D.D. Gajski and L. Ramachandran, "High-level Transformations for Minimizing Syntactic Variances," Proc. 30th DAC, pp. 413-418, 1993.

....In addition, once the SLIF was created, estimation times were on the order of milliseconds. To demonstrate SLIF s efficiency compared with lowergranularity formats, we compared SLIF with two other formats for the fuzzy logic controller. The SLIF AG required 35 nodes and 56 edges. The ADD format [19], which is similar to the Value Trace format, required over 450 nodes and 400 edges. The CDFG format required over 1100 nodes and 900 edges. The difference in complexity greatly affects the design algorithms (e.g. partitioning) that can be applied. For example, if an n 2 algorithm is to be ....

V. Chaiyakul and D. Gajski, "High-level transformations for minimizing syntactic variances," in DAC, 1993.

....controls register transfers in the datapath and generates signals for communication with the external world. There are several interdependent tasks that make up high level synthesis. The input executable specification is first compiled into an internal representation, such as one described in [14, 67, 68, 69]. The internal representation exposes control and data dependencies between arithmetic operations, such as between additions and comparisons. Allocation selects, from a register transfer component database, the storage, function and bus units to be used in the design. Scheduling maps operations to ....

V. Chaiyakul and D. Gajski, "High-level transformations for minimizing syntactic variances," in Proceedings of the Design Automation Conference, 1993.

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V. Chaiyakul, D. Gajski, and L. Ramachandran. High-level transformations for minimizing syntactic variances. In Design Automation Conference, June 1993.

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Chaiyakul, V., Gajski, D.D., and Ramachandran, L.: `High-level transformations for minimizing syntactic variances'. Presented at Design Automation Conf., Dallas, TX, 14--18 June 1993

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V. Chaiyakul, D. D. Gajski, and L. Ramachandran. "Highlevel Transformations for Minimizing Syntactic Variances", In Proc. Design Automation Conf., pages 413--418, June 1993.

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