D. D. Gajski, L. Ramachandran, "Introduction to High-Level Synthesis," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 44-54, Dec, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....are the underlying model of the POLIS design environment [Bal97] Finite State Machine with Datapath. In order to make it more suitable for data oriented systems, the FSM model has been extended by introducing a set of internal variables, thus leading to the concept of FSM with Datapath (FSMD) [Gaj94]. The transition relation depends not only on the present state and input signals but also on a set of internal variables. Though the introduction of variables in the FSMD model helps to reduce the number of states, the lack of explicit support for concurrency and hierarchy is a drawback because ....

D. D. Gajski and L. Ramachandran, "Introduction to High-Level Synthesis," in IEEE Design & Test of Computers, vol. 11, pp. 44-54, Winter 1994.

....This means that the initial model to a large extent determines whether an effective and satisfying implementation can be obtained or not, since only a limited part of the design space can be explored. The same problem is known in the context of high level synthesis as syntactic variance problem [34], which in general is unsolvable. 2.5 Introduction to Haskell Since the functional language Haskell is used to express the system models in ForSyDe, this section gives a small introduction to functional languages and Haskell in particular. Many examples are taken from A Gentle Introduction to ....

D. D. Gajski and L. Ramachdran. Introduction to high-level synthesis. IEEE Design & Test of Computers, 11(4), 1994.

....obtained by our approach on tested circuits range between 15 and 30 of the initial power dissipation. 1: Introduction High level synthesis is responsible for implementing a given behavioral description onto an RTL design typically by performing the tasks of scheduling, allocation and binding [1]. It has been demonstrated that decisions at the behavioral level have a significant impact on power consumption of the final hardware implementation [2, 3] In particular, for control dominated designs which typically consist of lots of sequential processes, scheduling is the most critical step ....

D. D. Gajski and L. Ramachandran, "Introduction to HighLevel Synthesis," IEEE Design and Test of Computers, pp.44-54, 1994.

....whilst trying to second guess the effects this will have on the synthesis tool. A number of researchers have suggested that source level transformation of behavioural specifications may be one way to open the black box, allowing more user guidance in the process of architectural exploration [54]. However, although a great deal of work has been carried out in this area [94, 143, 108] behavioural level transformations are currently not used in industrial high level synthesis. Other than the lack of tools to assist in the process, we believe that there are a number of reasons why ....

GAJSKI, D., AND RAMACHANDRAN, L. Introduction to high-level synthesis. Design & Test of Computers 11, 4 (1994).

....Hardware Resource Concurrency NFA Composition Cartesian Product and Pruning NFA Exploration Shortest Paths Performance Metrics Execution Sequences for Synthesis New NFA Models 6 1.4 Related Work 1.4. 1 High Level Synthesis ABSS is most related to work in high level synthesis [35] 39][40][66] 88] 137] High level synthesis is an automated process that transforms an algorithmic specification of a digital system s behavior into a hardware structure that implements the behavior. High level synthesis offers simple and fast design specification, short and highly automated design ....

....Input specification is typically a textual description of the desired behavior. It is often converted into a program dependence graph as described in section 1.2. Allocation is determination of the type and quantity of resources to implement a design for given performance and area constraints [40]. Scheduling is the partitioning of design behavior into control steps such that all operations in a control step execute in one clock cycle [40] Binding is assignment of operations, memory accesses, and interconnections from the behavioral design description to hardware units for optimal area ....

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D. Gajski and L. Ramachandran, "Introduction to High-Level Synthesis", IEEE Design & Test of Computers, pp.44-54, Winter 1994.

....[67] 69] As a concluding remark, we would like to point out that in the design flow of Fig. 1, operation scheduling is assumed to precede resource allocation. This may not always be the case in existing high level synthesis tools, where the order of execution of the two phases may be reversed [70], 71] also, it may happen that scheduling and allocation are performed simultaneously. If the latter is the case, the optimization problem must be formulated in a more global way, and the various aspects related to low power design that we have separately discussed for scheduling and allocation ....

D. D. Gajski and L. Ramachandran, "Introduction to high-level synthesis, " IEEE Design Test Comput. Mag., vol. 11, no. 4, pp. 44--54, Dec. 1994.

.... sufficiently efficient results, each design system is highly optimized for a particular application domain, parameterized target architecture, and minimization of a specific cost (area, speed, or power) In practice most of these systems concentrate on the scheduling, allocation, and binding tasks [Gaj94, WAC95]. Consequently these vertical systems only allow the exploration of a very small part of the total design space. Successful examples of such systems include the Cathedral compilers developed at IMEC [DeM86] the commercial DSP Station, and the Piramid [WBM90] and Phideo [LMW91, LMV94] compilers ....

....of 6 1996 Peter F.A. Middelhoek, Corrie Huijs, Gerhard E. Mekenkamp, Ewout W. Prangsma, Edwin Engels, Jaap Hofstede, Yhijs Krol retiming, pipelining, multi rate, loop, and scheduling transformations. Traditionally in high level synthesis most emphasis has been on scheduling and allocation steps [Gaj94, WaC95]. An overview of transformations used in TRADES can be found in [EMH93] In [Jan94] it is suggested that selecting a set of transformations for transformational design is relatively simple ; our experience however indicates the opposite. The set of primitive transformations needed in ....

D.D. Gajski, L. Ramachandran, Introduction to High-Level Synthesis, IEEE Design and Test of Computers, Vol. 11, No. 4, Winter 1994.

....representations are used in design of digital systems, especially because of their visualisation of information. In the transformational design system CAMAD an extended Petri net representation is used [9] Several kinds of mixed or separate data flow and control flow representations are defined [7, 8, 12]. In respect with DSP design several kinds of signal flow graph representations are used [1, 3, 6, 13] All graph representations are modelling hardware as hierarchical networks of processes or operational relational units. This modelling reflects the concurrent nature of hardware blocks. The ....

D. Gajski, Introduction to High-Level Synthesis, IEEE Design & Test, Vol. 11, Nr 4, Winter 1994, pp.44-54

....into a layout through a sequence of design tasks such as logic synthesis and layout synthesis. Resource constrained scheduling has been extensively studied by researchers in the VLSI CAD community and a large number of scheduling techniques have been proposed. These techniques are surveyed in [5], 9] Resourceconstrained scheduling is well known to be NP hard even when certain simplifying assumptions are made. Nevertheless, it is also well recognized that scheduling has a significant impact on the quality of the final design since it determines the configuration, resource requirements ....

D. Gajski and L. Ramachandran. "Introduction to High Level Synthesis, " IEEE Design and Test of Computers, pp. 44--54, Winter 1994.

.... (clock cycle) in which each operation will be executed, and assignment refers to the binding of each variable operation to one of the allocated registers functional units (FUs) Fast and accurate estimation is required to traverse the search space for possible solutions to each of these tasks [17,40]. A Control Data Flow Graph (CDFG) is typically used to represent a behavioral description. The data dependency edges in the CDFG reflect data dependencies of operands on the results of other operations, while control edges represent the flow of control. In this paper, we give an overview of ....

D.D. Gajski and L. Ramachandran, "Introduction to High-Level Synthesis, " IEEE Design & Test of Computers, Vol. 11, No.4, Winter 1994.

....required for preserving the implementation suggestion and are different from most other CDFG languages. 5.2. Implementation Suggestion While others consider the implementation suggestion an unwanted side effect of the specification process requiring a normalization step to dispose [Jan94, CGR93, Gaj94] we do not. On the contrary, the implementation suggestion may very well be intended by the designer and contain valuable pointers in the design space towards the optimal solution. This is especially so if the specification is written by an experienced designer. Furthermore, preserving the ....

....calculation of minimal bit widths to optimize area and timing. The structure of the algorithm in time and space can be altered by means of retiming, multi rate, loop, and scheduling transformations. Traditionally most emphasis in high level synthesis has been on scheduling and allocation steps [Gaj94, WaC95] An overview of transformations used in TRADES can be found in [EMH93] Figure 7 shows examples from the three categories. The tail merging transformation is used to merge identical operations in two mutually exclusive data paths, like the ones generated in the translation of ....

D.D. Gajski, L. Ramachandran, Introduction to High-Level Synthesis, IEEE Design and Test of Computers, Winter 1994.

....SCORE operators are synchronous, single clock entities, with their own state. Operators communicate only through designated I O streams. Operation is gated by data presence on the I O streams. As such, each operator can be viewed as a finite state machine with associated data path (i.e. FSMD [12]) In a multithreaded language, such as Java or C with an appropriate thread package, a SCORE operator would be an independent thread which communicates with the rest of the program only through singlereader, single writer I O streams. Specifically, SCORE does not have a global, shared memory ....

Daniel Gajski and Loganath Ramachandran. Introduction to High-Level Synthesis. IEEE Design and Test of Computers, 11(4):44--54, 1994.

....be passed to the software or to an external system (e.g. through a Digital to Analog Converter for driving some nonelectronic instrument) Since direct control of such data flows is not performed by software, a control unit that incorporates a state machine has also to be built in hardware. In [8] a description format for em Finite State Machines with Data Path Model is presented and some synthesis aspects are discussed. CHAPTER 3 DESIGN 23 Public P8641 HUB INF DS P D1.3 b2 Methodology INSYDE WP1 HUB 400 Version 2 Operator Operand 1 Operand N Result(s) Perform Operation Control ....

D. S. Gajski, L. Ramachandran. Introduction to High-Level Synthesis. IEEE Design & Test of Computers, pp. 44-54, 1994.

....are described in the following sections. 5.1. 2 VHDL Behavioral Description and Simulation VHDL has the advantage as a specification and synthesis language in that it can describe hardware at various levels of abstraction, from the architectural (behavioral) level down to the structural level [52], 53] It also provides a generic design entry platform in that the design may be created in VHDL and the target implementation technology chosen later [54] In this case, the synthesis tool can be used to map the design to any specific target technology, thus forgoing the task of a complete ....

....behavioral form, devoid of implementation details, and then synthesize the design using CAD tools. This achieves higher productivity gains since the design process is moved to higher abstraction levels, where designers can specify, model, verify, synthesize, simulate and debug designs in less time [52]. It is for these reasons, plus the general Controller Logic Design and Verification 73 advantages of automated synthesis, that VHDL synthesis tools were employed in the design of the CRAM controller. The choice of VHDL over Verilog as the description language for the design was justified by the ....

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D. Gajski, "Introduction to High-Level Synthesis", IEEE design and Test of Computers, Winter, 1994, pp 45-54.

....in the case of ABR traffic. ffl The timing unit block is used to control the ABR traffic parameter such as the Allowed Cell Rate (ACR) Decrease Time Factor (ADTF) and Trm. 3 Behavioral Specification Behavioral synthesis is the process of refining a specification into an RTL model [11] [5]. The main difference between behavioral and RTL model is related to timing. At the RT level a description details the behavioral of the design at the clock cycle level. A behavioral model is generally specified in terms of computation steps. The synchronization between the behavioral model and ....

....made of processes communicating with the external world through wait statements. In this case the computation step correspond to the code between two wait statements. The main task of behavioral synthesis is to split these computation steps into clock cycles in order to produce an RTL model [5], 11] 7] Of course the behavioral specification of complex systems like the ATM Shaper may be composed of interconnected blocks. The specification step is then generally composed of two steps, partitioning of the system into separate modules and describing the behavior of these modules and ....

D. D. Gajski and L. Ramacahndran. Introduction to high level synthesis. IEEE Design and Test Computer, October 1994.

....Flow Graphs ( Gja91] allow only simple components such as arithmetic operations, counters, comparators, etc. to be design building blocks. Another disadvantage of the flow graphs is that they are very far from the real architectural implementation. The FSMD (FSM with Data path) model ( GR94] is more powerful to express at once a behavioral specification and architecture realization. The FSMD model differs from simple FSM in the introduction of storage variables. The FSMD outputs include storage elements assignments. The storage variables are realized as storage units of a data path ....

Gajski Daniel D. and Ramachandran Loganath. Introduction to High-Level Synthesis. In IEEE Design & Test of Computers, volume Winter 1994, pages 44--54, 1994.

....enhance design re usability. 1.2 Related Work It is a common practice for synchronous circuits to be formally modeled and automatically synthesized. There are many existing tools which support automatic translation of an algorithmic level specification to a register transfer level representation [22]. The use of such models and automated tools for asynchronous circuits has been limited to synthesizing control circuitry. Thus, many systems exist for the synthesis of untimed asynchronous control circuits [27] A number of different styles for designing asynchronous control circuits exist. One ....

Gajski, D. Introduction to High-Level Synthesis. IEEE Design & Test of Computers, 1994.

....solve those problems. 1. INTRODUCTION High level synthesis (sometimes called behavioral synthesis) is the design task of mapping an abstract behavioral description of a digital system onto a registertransfer level design to implement that behavior. Introduced in the first article in this series [Gajski94], high level synthesis has the potential to greatly improve both designer productivity and design space exploration. As defined in that introductory article, the three central synthesis tasks in a typical high level synthesis system are the following: scheduling determining the sequence in ....

Daniel D. Gajski and Loganath Ramachandran, "Introduction to High-Level Synthesis", IEEE Design & Test, pages 44-- 54, Winter 1994.

....computed in the corresponding registers of the data part are equal. 2. The FSMD formalization The model M1 of the specification, extracted from the initial VHDL, is strongly inspired by Gajski s Finite State Machine with Datapath model. The original FSMD was defined in a semi formal way [GR94], sufficient for algorithmic purposes but not for formal proofs. Our contribution is a more mathematical definition of the notions of assignments and statusses. Throughout the rest of this paper, we use the following notations : S is the set of control states, S = s 1 , s 2 , s a I is ....

D.Gajski, L.Ramachandran: "Introduction to Highlevel Synthesis", IEEE Design & Test of Computers, vol. Winter, 1994.

....mentioned, the circuit is called Abstract FSM before allocation and Final RTL architecture after allocation. 4. 1 Mathematical model for the Abstract FSM The mathematical model corresponding to the abstract FSM is strongly inspired by Gajski s Finite State Machine with a data path (FSMD) model ([GR94]) The main idea of the FSMD model is the introduction of variables stored in registers and memories (we call them storage variables) Each variable replaces thousands states in a classical FSM model. For example, a 32 bit variable reduces the FSM state space by 2 32 . We refined Gajski s ....

Daniel D. Gajski and Loganath Ramachandran. Introduction to High-Level Synthesis. In IEEE Design & Test of Computers, volume Winter, pages 44--54, 1994.

....with the RTL based methodology and with the proposed High Level Synthesis based methodology. 1. 2 Taxonomy of High Level Synthesis Designs The basic function of HLS is the mapping of a behavioral description of a digital system onto an RTL design consisting of a data path and a control unit [4]. The main steps executed by HLS are scheduling and allocation. Most existing HLS tools are specialized for a restricted class of applications. According to Gajski [4] hardware designs may be classified in three categories: ffl control dominated designs represented by Control Flow Graph; ffl ....

....HLS is the mapping of a behavioral description of a digital system onto an RTL design consisting of a data path and a control unit [4] The main steps executed by HLS are scheduling and allocation. Most existing HLS tools are specialized for a restricted class of applications. According to Gajski [4], hardware designs may be classified in three categories: ffl control dominated designs represented by Control Flow Graph; ffl data dominated designs represented by Data Flow Graph; ffl control data dominated designs represented by ControlData Flow Graph. 1.2.1 Control Flow Dominated ....

D.D. Gajski and L. Ramachandran. Introduction to HighLevel Synthesis. IEEE Design and Test of Computers, pages 44--54, 1994.

....register transfer components such as registers, multiplexors, and ALU s. Such a structure usually consists of two parts: a controller implementing a finite state machine, and a datapath executing arithmetic operations. We refer to such a structure as a finite state machine with datapath, or FSMD [1, 66]. The controller controls register transfers in the datapath and generates signals for communication with the external world. There are several interdependent tasks that make up high level synthesis. The input executable specification is first compiled into an internal representation, such as ....

D. Gajski and L. Ramachandran, "Introduction to high-level synthesis," in IEEE Design & Test of Computers, 1994.

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D. D. Gajski, L. Ramachandran, "Introduction to High-Level Synthesis," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 44-54, Dec, 1994.

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D. Gajski, L. Ramachandran: "Introduction to High-level Synthesis", IEEE Design and Test of Computers, Vol. Winter, 1994, pp.44-54

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Gajski, D., Ramacahndran, L.: Introduction to high level synthesis. IEEE Design and Test Computer, October 1994.

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D. D. Gajski and L. Ramacahndran. Introduction to high level synthesis. IEEE Design and Test Computer, October 1994.

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D.D. Gajski. Introduction to high-level synthesis. IEEE Design and Test of Computers, pages 44--54, Winter 1994.

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Gajski, D., Ramacahndran, L.: Introduction to high level synthesis. IEEE Design and Test Computer, October 1994.

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D. Gajski, Introduction to High-Level Synthesis, IEEE Design & Test, Vol. 11, Nr 4, Winter 1994, pp.44-54

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Gajski 94 D. D. Gajski, and L. Ramachandran, "Introduction to High-level Synthesis," IEEE Design and Test of Computers, Vol. 11, No. 4, pp. 44-54, Winter, 1994.

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D. S. Gajski, L. Ramachandran. Introduction to High-Level Synthesis. IEEE Design & Test of Computers, pp. 44-54, 1994.

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