G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 274--277, IEEE, 1987.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....identified: di#erences in clock speeds, signalling conventions, sequencing of data and data width or data type mismatches. Additional issues arising in interface construction are optimising latency and bu#er sizes, resolving non determinism and preserving timing requirements. Borriello and Katz[4] use timing diagram specifications of protocols to construct event graphs and then generate a logic circuit which behaves as a transducer. Their technique requires that data buses have the same names and that the designer provide the information for correct merging of event graphs. Gajski et ....

Gaetano Borriello and Randy H. Katz. Synthesis and optimization of interface transducer logic. Proceedings of the International Conference of Computer Aided Design, November 1987.

....to allow programmable logic to be embedded in key modules of a system and provide on line programmability to change hardware functionality. Tools for distributed hardware control synthesis to allow dynamic binding of hardware resources [16] and synthesis of protocols to low latency hardware [8, 14, 15] have been successfully demonstrated. With these CAD and synthesis capabilities, embedded programmable logic can be inserted into the key parts of systems, and used to alter behavior dramatically with modest performance overhead. 2 System Architecture Organization As mentioned earlier, the ....

Borriello, G., and Katz, R. Synthesis and Optimization of Interface Transducer Logic. In Proceedings of the IEEE International Conference on Computer-Aided Design (Nov. 1987), pp. 274--277.

....1 Design 2 a) Channel Interface R A D R A D Clk R A D b) Channel Protocol Design 1 R A D R A D Design 2 P1 P2 P3 Design 1 Design 2 P1toP3 P1 P3 c) Composition and Decomposition of Protocols 2.2. Formal descriptions: Extended Timing Diagrams Original work by Borrielo [97, 98, 99] introduced the concept of event graphs for establishing the correct synchronization and data sequencing between two protocols. In 1987, Borrielo and Katz introduced the concept of transducer synthesis [97] A transducer is defined as the glue logic that connects two circuit blocks with ....

....2.2. Formal descriptions: Extended Timing Diagrams Original work by Borrielo [97, 98, 99] introduced the concept of event graphs for establishing the correct synchronization and data sequencing between two protocols. In 1987, Borrielo and Katz introduced the concept of transducer synthesis [97]. A transducer is defined as the glue logic that connects two circuit blocks with incompatible interfaces. As an input description they used timing diagrams of the two interfaces. Timing diagrams with imposed timing constraints are very common in data sheets for describing the interfaces in ....

G. Borrielo, R. H. Katz, "Synthesis and Optimization of Interface Transducer Logic", In Proc. of the ICCAD'87, 1987.

....in the form of parameters such as arbitration priorities, block transfer sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proc. Int. Conf. Computer Design, Nov. 1987.

....improvement in circuit complexity and performance compared to DI, SI or QDI circuits [78] However, as with fundamental mode circuits, the correct operation of these circuits depend on the validity of the delay bounds in the actual implementation. The reader is referred to the literature [61, 8, 43] for a more thorough discussion of other practical asynchronous design styles that make use of bounded delay assumptions. 1.3 Why Approximate Timing Analysis We have seen above that practical asynchronous circuits depend on certain timing con straints for their correct operation. Since ....

....that the naive strategy for detecting or dering of transitions is used. Since the circuit is symmetric with respect to A1 and A2 GATE: DELIA1] 1 o [1,4] 2,2] l 1 0 ) Xl o [2,2] 1,4] 1,2] 2,2] OXO 1 0 1 A1 1 2 3 4 5 6 7 8 9 10 [0,0] 1,1] 2,5] 2,5] 4,7] 4,9] 1,5] 2,7] [2,8] [4,10] 4,12] Gate delays are [min, max] Wires have zero delay. Figure 2.8: Basic min max algorithm applied to example circuit from [50] for the given input stimulus, the delay bounds from A2 to the internal gates are identical to those from A1. The results are more pessimistic than the ....

[Article contains additional citation context not shown here]

G. Bordello and R. H. Katz. Synthesis and optimization of interface transducer logic. In Proceedings of the 1987.

....into an infinite acyclic graph [3] We have derived a sufficient condition which breaks the infinite acyclic graph into a finite acyclic graph so that these algorithms can be used to correctly detect redundant circuitry. Using timing constraints to simplify asynchronous circuits is not a new idea [4] [5] however, most of these techniques were based on adding delay elements to avoid circuit hazards. We will show that hazard free timed circuits can be synthesized without suffering any further delay compared with speed independent circuits, while using the timing constraints to reduce the ....

Gaetano Borriello and Randy H. Katz. "Synthesis and Optimization of Interface Transducer Logic". In Proceedings IEEE 1987.

....hardware and software synthesis tools to generate the final system design. Hardware synthesis is done using program Hebe [1] and software component is generated using available C compiler for the target processor. Synthesis of interface logic may also be obtained using techniques indicated in [12] [13]. 4.1 Interface As mentioned earlier, the hardware software interface depends upon the corresponding data transfer requirements imposed on the system model. In the case of known data rates where (nonblocking) synchronous data transfers are possible, the interface contains an interface buffer ....

G. Borriello and R. Katz, "Synthesis and Optimization of Interface Transducer Logic," in Proceedi.gs of the IEEE Tra.sactio.s o. CAD/ICAS, Nov. 1987.

....iterations. These operations have execution delays that are not known at compile time, or equivalently, their delays are unbounded. Second, real time ASIC applications require the specification of detailed timing constraints in the hardware model and their enforcement in the synthesis process [14] [15] [16] Timing constraints specify upper and lower bounds on the time separation between two operations. They can be applied, for example, to control the time gap between a read and a write of an external bus, or to synchronize two write operations. We present in this paper a scheduling algorithm ....

G. Bordello and R. Katz, "Synthesis and optimization of interface transducer logic," in Proceedings of the International Conference on Computer-Aided Design, (Santa Clara, CA), pp. 56-60, Nov. 1987. 41

....them into a graphical representation, the TEL structure. Then, timing analysis algorithms are applied to nd the reachable state space of the system, which is used to derive the circuit implementation. 1.2.2 Synthesis There exist some systematic techniques for the design of timed circuits. In [17], Borriello describes a method which uses timing information in the design of transducers, interfaces between synchronous and asynchronous circuits. In [46] Lavagno develops a synthesis technique which uses methods similar to Chu [28] and Meng [53] to derive a complex gate level implementation ....

Borriello, G., and Katz, R. H. Synthesis and optimization of interface transducer logic. In Proceedings IEEE

....improvement in circuit complexity and performance compared to DI, SI or QDI circuits [78] However, as with fundamental mode circuits, the correct operation of these circuits depend on the validity of the delay bounds in the actual implementation. The reader is referred to the literature [61, 8, 43] for a more thorough discussion of other practical asynchronous design styles that make use of bounded delay assumptions. 1.3 Why Approximate Timing Analysis We have seen above that practical asynchronous circuits depend on certain timing constraints for their correct operation. Since component ....

....for detecting ordering of transitions is used. Since the circuit is symmetric with respect to A1 and A2 CHAPTER 2. MIN MAX TIMING SIMULATION 23 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 DEL[A1] GATE: A1 [0,0] 1 [1,1] 2 [2,5] 3 [2,5] 4 [4,7] 5 [4,9] 6 [1,5] 7 [2,7] 8 [2,8] 9 [4,10] 10 [4,12] 1,5] 1,4] 1,4] 2,2] 0X0 [2,2] 1,1] 1,2] 1,3] 2,2] 2,2] 0X0 A1 A2 5 1 2 3 4 6 7 8 9 10 Y1 Y2 Gate delays are [min, max] Wires have zero delay. Figure 2.8: Basic min max algorithm applied to example circuit from [50] CHAPTER 2. MIN MAX ....

[Article contains additional citation context not shown here]

G. Borriello and R. H. Katz. Synthesis and optimization of interface transducer logic. In Proceedings of the

....during interface synthesis, and thus timing verification techniques, which can prove that the system timing behavior is correct, promise to be effective tools to facilitate the design process. As a matter of fact, interface timing verification research has attracted considerable attention recently [16, 17, 20, 48, 49, 67, 72, 114]. 5 It is our tenet that in order to verify a hardware interface between two modules, one does not need to know all the details of the implementation of the modules. What is needed is the specification of each module s interface behavior. This specification is usually given in textual form ....

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proceedings of the International Conference on Computer-Aided Design, pp. 274--277, 1987.

....etc. usedbythechannels buses in the selected topology. The VSI Alliance on chip bus working group [14] has recognized that a multitude of bus protocols will be needed in order to serve the wide range of SOC communication requirements. Finally, there is a body of work on interface synthesis [15, 16, 17, 18, 19, 20, 21, 22], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proc. Int. Conf. Computer Design, Nov. 1987.

....looked up. Alternatively, a bus may be flexible, in which case the best width and protocol must still be determined; algorithms and techniques have been reported in [37] 38] After determining the protocol to meet design constraints, structure can be created for the protocol using techniques in [39] [41] GAJSKI et al. SPECSYN: AN ENVIRONMENT SUPPORTING THE SER PARADIGM 95 Fig. 15. Refined fuzzy logic controller VHDL partial specification. B. Memories Another task is memory refinement associated with the implementation of variables assigned to memories. The variable accesses must be ....

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proc. Int. Conf. Computer-Aided Design, 1987.

....what should happen once an input has been recognized, i.e. the data that should be output. A compiler then synthesizes the automaton. Many methods dealing with Interface Protocol synthesis have been presented over the last decade since Borrielo presented his transducer synthesis technique in 1987 [2]. Most of the methods are based on procedural HDLs or a control flow graphs derived from a procedural HDL. However, describing a communication protocol in a procedural style is not always convenient although calling an abstract send receive function may be. Protocols have long been modelled using ....

G. Borrielo, R. H. Katz, "Synthesis and Optimization of Interface Transducer Logic", In Proc. of the ICCAD'87, 1987.

....in the form of parameters such as arbitration priorities, transfer block sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter component communication. Finally, there is a body of work on interface synthesis [16, 17, 18, 19, 20, 21, 22, 23], which deals with automatically generating efficient hardware implementations for component to bus or component to component interfaces. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves. In summary, we believe ....

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proc. Int. Conf. Computer Design, Nov. 1987.

.... The following discuss the anatomy of compilation and issues [Haa91, KW88] Hardware software interface specification and analysis Modeling,synthesis and analysis of interface between system components (particularly, hardware and software) has been a subject of research for quite some time [BK87, COB92, FKCD93, KLM93, AB91] In recent years, the focus seems to have shifted to asynchronous hardware elements to effectively represent and synthesize interface [MD92] Hardware software system architectures The choice of a suitable architecture for hardware software systems is an open issue. ....

G. Borriello and R. Katz. Synthesis and Optimization of Interface Transducer Logic. In Proceedings of the IEEE International Conference on Computer-Aided Design, pages 274--277, November 1987.

....generates the signals necessary to satisfy the protocols of either component it is linking. This object can then be realized as a FSM and may be synthesized as another hardware component, merged with another synthesizable component or be translated to software running on an associated processor [4]. D. Inline Channel. Behavior that has been partitioned and allocated to an undefined component may have its communication functionality inlined. Namely, the behavior or logic necessary to initiate a communication transaction, formerly located in the channel object is placed inside the partition ....

G. Borriello, R.H. Katz. "Synthesis and Optimization of Interface Transducer Logic." Proceedings of the International Conference on

....Integrated Systems, Stanford University and the Semiconductor Research Corporation, Contract no. 92 DJ 205. The authors are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305. Methods have been proposed to use timing constraints to synthesize timed circuits [9] [10] however, most techniques apply timing constraints after synthesis only to verify that hazards do not exist. If hazards are detected, delay elements are added to avoid them, degrading the performance of the implementation. It was shown in [4] that the more conservative speed independent ....

Gaetano Borriello and Randy H. Katz. "Synthesis and Optimization of Interface Transducer Logic". In Proceedings IEEE 1987 ICCAD Digest of Papers, pages 274--277, 1987.

....features such as multiple transfer modes and well specified timing constraints, which are not supported by Narayan s approach. Other approaches for interfacing modules with incompatible protocols have been proposed in the past. Notable among these is the transducer synthesis approach by Borriello [1], in which glue logic (also known as the transducer) is automatically generated for two incompatible protocols specified as timing waveforms. Sun s work [7] on generating interface modules used techniques similar to Borriello s; however, it raised the design abstraction level by allowing the ....

G. Borriello and R. Katz. Synthesis and optimization of interface transducer logic. In Proceedings of the IEEE International Conference on Computer Aided Design, pages 274--277, 1987.

....of perfectly matched data rates a synchronous non blocking protocol is selected. After selecting transfer protocols for different data transfers across the hardware and software models, the interface circuitry can be synthesized using asynchronous and synchronous logic synthesis techniques [15] [16]. For a description of the interface architecture the reader is referred to [7] DLX Assembly Code SLIF Netlist Implements: a. Interface protocol between models b. event driven simulation of multiple models c multiple clocks and clock rates between models Ariadne System Graph Model (Gate level ....

....of Graphics Controller Example 2: Specification of the graphics controller interface (Figure 6) model gc io 1.0 DIR GraphicsController; model ccoord mercury 5.0 DIR gcircle; model lcoord mercury 5.0 DIR gline; model mp dlx 1.0 DIR main; model CF mercury 1. 0 DIR control; queue [1] lqueue[16], cqueue[16] queue [3] controlFifo[2] CF.r[0:0] lcoord.run[0:0] ccoord.run[0:0] gc.run[0:0] CF.RESET = lcoord.RESET = ccoord.RESET = gc.RESET; CF.lrq[0:0] lqueue.empty; CF.lak[0:0] mp.0xff004 rd; CF.crq[0:0] cqueue.empty; CF.cak[0:0] mp.0xee004 rd; mp.0xee004[0:0] ....

[Article contains additional citation context not shown here]

G. Borriello and R. Katz, "Synthesis and Optimization of Interface Transducer Logic," in Proceedings of the IEEE Transactions on CAD/ICAS, Nov. 1987.

....and techniques [4,50] In the 1980s work on high level synthesis started to spread from the academic community to industry. High level synthesis systems are now producing manufacturable chip designs for applications such as signal processing [10] pipelined processors [31] and interfaces [7]. However, there are still many unanswered questions related to such issues as specification, input output, designer intervention, complex timing constraints, and the relation of synthesis to the overall design and fabrication process. The paper starts with the description of high level synthesis ....

Borriello G. and Katz R. H. (1987) Synthesis and Optimization of Interface Transducer Logic. Proc. ICCAD, p. 274-277.

....hardware resources used during allocation. Second and equally important, it fixes the relative timing of operators and thus the satisfaction of timing constraints. 2,3] Timing constraints are important because they allow designers to specify both desired performance and interface information [2,4]. Fig. 1 illustrates the scheduling problem using a typical CDFG, which is a directed graph in which nodes represent operators and edges represent ordering dependencies between operators. 1 Source and sink nodes represent the beginning and end of activities in the graph. Edges between nodes ....

G. Borriello and R. Katz, "Synthesis and Optimization of Interface Transducer Logic", Proceedings ICCAD-87, pp. 274-277, November, 1987.

No context found.

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, pp. 274--277, IEEE, 1987.

No context found.

G. Borriello and R. H. Katz, "Synthesis and optimization of interface transducer logic," in Proc. Int. Conf. Computer Design, Nov. 1987.

No context found.

Borriello, G., and Katz, R. Synthesis and Optimization of Interface Transducer Logic. In Proceedings of the IEEE International Conference on Computer-Aided Design #Nov. 1987#, pp. 274#277.

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