J. Gong, D. Gajski, and S. Narayan, "Software estimation from executable specifications, " Journal of Computer and Software Engineering, Vol. 2, No. 3, pp. 239258, 1994. 117  Home/Search   Document Details and Download   Summary   Related Articles   Check

....we focus in the sequel on software performance estimations of DSP processors that are well suited to be integrated into dedicated HW SW mixed systems. 2. Problem addressed Performance estimations of CISC processors that do not contain pipelining and caching may lead to accurate results [8]since factors of performance pertubations are minimized. Notice that the estimation of the software execution time includes both the capabilities of the processor to execute the program of the application and also the ability of the compiler to produce an optimized assembly code. Current ....

GONG J. , GAJSKI D., NARAYAN S., Software estimation from executable specifications. Journal of Computer and Software Engineering. 1994.

.... processors (processor graphs) This co design scheme includes behavioral decomposition, processor allocation and communication transformation ( 12] 27] Most of the existing partitioning methods restrict the cost function to parameters such as real time constraints ( 8] 27] or cost ([13]) In this paper we will restrict our discussion to codesign tools of the third category. Coware ( 10] handles very well multiprocessor codesign during the latest design phases. However, it starts from a C VHDL where partitioning is already done. Specsyn ( 12] is a precursor for the co design ....

J. Gong, D. Gajski, S. Narayan, Software Estimation from Executable Specifications, Proceedings European Design & Automation Conference (EuroDAC), IEEE CS Press, Grenoble, France, September 1994.

....require balancing numerous competing implementation properties including size, cost, performance, power, reliability, and design time. Researchers have been developing tools to analyze and optimize these properties. These include tools such as [3] that aid in hardware synthesis and tools such as [2] that aid in software design. Some of our own work [6] has involved tools to analyze and optimize power consumption. A more comprehensive survey of power estimation techniques in available in [4] As developers of embedded system CAD tools, we have noted that many designers are still reluctant to ....

J. Gong, D. Gajski, and S. Narayan, "Software Estimation from Executable Specifications," Journal of Computer and Software Engineering, v. 2, no. 3, pp. 239-258, 1994.

....each one targeted to a specific processor. Clearly, such a system is economically and computationally expensive since we must have a compiler and an estimator for each different processor, but it produces very accurate performance metrics. 4. 2 Generic estimation model In this model, proposed in [39], instead of using specific compilers and estimators for each different target processor, a behavior is first compiled into a set of generic instruction set. The estimator evaluates, then, software performance for the target processor in according to the information made avalaible by ....

J. Gong, D. Gajski, S. Narayan, "Software estimation from executable specifications", Journal of Computer and Software Engineering, 1994.

....the addressing modes of the instructions determined by data dependencies and a greedy register allocation scheme. The execution times of the generic instructions are then determined from a technology file corresponding to the target microprocessor. This is similar to the approach described in [3], where good estimation results are reported, and the same technology files for the 8086, 80286, 68000 and 68020 microprocessors are used. The execution time of the DFG is obtained by summing the execution times of the generic instructions and multiplying the sum with the profiling count for the ....

Jie Gong, Daniel D. Gajski, and Sanjiv Narayan. Software estimation from executable specifications. Technical Report ICS-93-5, Dept. of Information and Computer Science, University of California, Irvine, Irvine, CA 92717-3425, March 8 1993.

....(9 EA1) mov word ptr[bp offset3] ax (10) generic instruction dmem3 dmem1 dmem2 execution time size . 22 8086 instructions 68020 instructions Generic instruction Technology file for 68020 Texhnology file for 8086 Figure 18. Execution time of a generic instruction for different processors([17], page 6, fig.3) in [17] where good estimation results are reported, and we use the same technology files for the 8086, 80286, 68000 and 68020 microprocessors. The advantages as compared to an approach where a specific compiler is used for each processor is that it is not necessary to make find a ....

....ax (10) generic instruction dmem3 dmem1 dmem2 execution time size . 22 8086 instructions 68020 instructions Generic instruction Technology file for 68020 Texhnology file for 8086 Figure 18. Execution time of a generic instruction for different processors( 17] page 6, fig.3) in [17], where good estimation results are reported, and we use the same technology files for the 8086, 80286, 68000 and 68020 microprocessors. The advantages as compared to an approach where a specific compiler is used for each processor is that it is not necessary to make find a new compiler for each ....

Jie Gong, Daniel D. Gajski, and Sanjiv Narayan. Software estimation from executable specifications. Technical Report ICS-93-5, Dept. of Information and Computer Science, University of California, Irvine, Irvine, CA 92717-3425, March 8 1993.

.... I) Examples of such algorithms include group migration [6] and simulated annealing [7] Since it is not feasible to implement the hardware and software components in order to determine a cost for each possible partitioning generated by an algorithm, we assume that fast estimators are available [8, 9, 10]. 3 Solving the hardware software partitioning problem 3.1 Greedy algorithms One simple and fast algorithm starts with an initial partition, and moves objects as long as improvement occurs. Such an algorithm is shown below. It uses a procedure Move(P; f i ) which returns a new partitioning P ....

....The description is decomposed to the granularity of tasks, i.e. processes, procedures, and optionally to statement blocks such as loops. Large data items (variables) are also treated as functions. Estimators of hardware size and behavior execution time for both hardware and software are available [8, 9]. These estimators are especially designed to be used in conjunction with partitioning. In particular, very fast and accurate estimations are made available through special techniques to incrementally modify an estimate when a function is moved, rather than reestimating entirely for the new ....

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J. Gong, D. Gajski, and S. Narayan, "Software Estimation from Executable Specifications, " in Journal of Computer and Software Engineering, to appear.

.... 15 x x x x x x x[0] x[1] x[2] b[0] b[0] b[1] b[2] y[0] y[1] y[2] b[0] b[1] x[1] x[0] x[0] x x x x x[15] b[0] b[1] b[2] b[3] x[14] x[13] x[12] y[15] x x x x x[3] b[3] y[3] b[0] b[1] b[2] x[1] x[0] x[2] x x x x b[0] b[1] b[2] b[3] x[4] x[3] x[2] x[1] y[4] Figure 6: Horizontal Slicing of FIR Filter Computation 16 x x x x x x x[0] x[1] x[2] b[0] b[0] b[1] b[2] y[0] y[1] y[2] b[0] b[1] x[1] x[0] x[0] x x x x x[15] b[0] b[1] b[2] b[3] x[14] x[13] x[12] y[15] x x x x x[3] b[3] ....

.... x x x[0] x[1] x[2] b[0] b[0] b[1] b[2] y[0] y[1] y[2] b[0] b[1] x[1] x[0] x[0] x x x x x[15] b[0] b[1] b[2] b[3] x[14] x[13] x[12] y[15] x x x x x[3] b[3] y[3] b[0] b[1] b[2] x[1] x[0] x[2] x x x x b[0] b[1] b[2] b[3] x[4] x[3] x[2] x[1] y[4] Figure 6: Horizontal Slicing of FIR Filter Computation 16 x x x x x x x[0] x[1] x[2] b[0] b[0] b[1] b[2] y[0] y[1] y[2] b[0] b[1] x[1] x[0] x[0] x x x x x[15] b[0] b[1] b[2] b[3] x[14] x[13] x[12] y[15] x x x x x[3] b[3] y[3] b[0] b[1] b[2] ....

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J. Gong, D. Gajski, and S. Narayan, "Software estimation from executable specifications", UC Irvine, Dept. of ICS, Technical Report 93-5, 1993.

....calculated by following equation: execution(S ) X b i 2S execution(b i ) Theta freq(b i ) 1) where b i is basic block. This report takes the same approach in [1] to do software performance estimation for TLCS R3900 processor. In basic block estimation, we adapt the generic estimation model[3], which is shown in Figure 2. The system specification was compiled into generic three address instructions. For each processor, there is a technology file providing the timing and instruction size of each generic instruction. Then the execution time of basic block can be calculated as follows: ....

....and size information 68000 instruction set timing and size information TLCS R3900 instruction set timing and size information Figure 2: Generic estimation model cessor with certain exceptions. Since the generic estimation model has shown good results in estimation for non pipelined processor in[3], we now extend it to measure the performance of TLCSR3900, which is a pipeline processor. Fundamentally, the overlap time of pipeline instruction can be reflected in execution(B) X I j 2B (time(I j ) Gamma pipe depth 1) pipe depth Gamma 1 (3) but the result is not accurate due to ....

J. Gong, D. Gajski, and S. Narayan, "Software estimation from executable specifications." UC Irvine, Dept. of ICS, Technical Report 93-05,1993.

....The metrics file gives the number of instruction cycles and the number of bytes required to execute each of a list of 3 address generic instructions on that processor. This information characterizes a processor and is required to estimate the execution time of a behavior on a specific processor [7]. The clock constraint of 10 ns indicates that each of the hardware behaviors will operate at a clock frequency of 100 MHz and this clock value is used while estimating the area and delay of the hardware behaviors. Finally, the PS delay constraint indicates that a new sample of input data will be ....

....constraint = 4000 ns Initial processor allocation = powerPC 3800 Hardware software Partition 3100 900 Figure 7: The processor execution time (PET) table and hardware software partition for CFG and software library in Figure 1. The execution time is determined by invoking a software estimator [7] [11] which translates the VHDL code of the given behavior to a list of three address generic instructions, and then obtains the number of instruction cycles required to execute each of the three address instructions from the metrics file associated with the processor. A sum of the instruction ....

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Jie Gong, Daniel Gajski, and Sanjiv Narayan. Software estimation from executable specifications. In The Journal of Computer and Software Engineering, 1994.

....In [9] estimates are obtained by roughly synthesizing hardware for each group of functions, and a special data structure is used that permits rapid, incremental modification of the hardware as functions are moved between groups. For software performance estimation, techniques in [49] and [50] use dynamic profiling to estimate execution time during hardware software partitioning. Techniques in [51] and [52] perform path analysis to determine minimum or maximum execution times, the latter with the help of user annotations. In [53] methods are described for reasoning about program ....

J. Gong, D. Gajski, and S. Narayan, "Software estimation from executable specifications, " in Journal of Computer and Software Engineering, 1994.

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J. Gong, D. Gajski, and S. Narayan, "Software estimation from executable specifications, " Journal of Computer and Software Engineering, Vol. 2, No. 3, pp. 239258, 1994. 117

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J. Gong, D. Gajski, S. Narayan, "Software Estimation from Executable Specifications," Journal of Computer and Software Engineering, 1994.

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