| A. Chandrakasan, S. Sheng, and R. Brodersen. Low-power cmos digital desig. IEEE Journal of Solid-State Circuits, 27(4):473--484, April 1992. |
.... scheduling problems to obtain power energy savings [5, 3, 6, 7] It has been shown that maximal energy saving is achieved by running the processor at the slowest possible constant speed, rather than running tasks at full processor speed and changing the processor to a lower power mode when idle [2]. Hong et al. [5] proposed a heuristic for scheduling real time tasks on a single variable voltage processor. Shin [3] exploited both execution time variation and idle time intervals for fix priority tasks. Shin s algorithm in [6] determines the lowest maximum processor speed for each job to ....
A. Chandrakasan, S. Sheng, and R. Brodersen. Low-power cmos digital desig. IEEE Journal of Solid-State Circuits, 27(4):473--484, April 1992.
.... many are based on real time task scheduling cores [13, 38, 39, 36] It has been shown that maximal energy saving is achieved by running the processor at the slowest possible constant speed, rather than running tasks at full processor speed and changing the processor to a lower power mode when idle [6]. Hong et al. [13] proposed a heuristic for scheduling real time tasks on a single variable voltage processor. Shin [38] exploited both execution time variation and idle time intervals for fix priority tasks. Shin s algorithm in [39] determines the lowest maximum processor speed for each job to ....
A. Chandrakasan, S. Sheng, and R. Brodersen. Low-power cmos digital desig. IEEE Journal of Solid-State Circuits, 27(4):473--484, April 1992.
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