Y. S. Kim, W. S. Kang, and J. R. Choi. Implementation of 1024-bit modular processor for RSA cryptosystem. In Proceedings of Asia-Pasific Conference on ASIC (AP-ASIC), Cheju Island, Korea, August 28-30 2000. Home/Search Document Not in Database Summary Related Articles Check |
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Hardware Implementation of Elliptic Curve Processor over GF(p) - Örs, Batina, Preneel (Correct)
....His method proved to be very e#cient and is the basis of many implementations of modular multiplication, both in software and hardware. In this paper we look at a hardware implementation. E#cient implementation of Montgomery modular multiplication (MMM) in hardware was considered by many authors [7, 13, 33, 22, 17, 24, 34, 27, 14, 25, 28]. A systolic array architecture is one possibility for implementations of public key cryptography in hardware. Various solutions for systolic arrays were proposed, for example [8, 12, 11, 32, 13, 15, 29, 35, 26, 3, 9, 31, 36, 4, 30, 2] In this work we combine a systolic array architecture, which ....
Y. S. Kim, W. S. Kang, and J. R. Choi. Implementation of 1024-bit modular processor for RSA cryptosystem. In Proceedings of Asia-Pasific Conference on ASIC (AP-ASIC), Cheju Island, Korea, August 28-30 2000.
Hardware Implementation of a Montgomery Modular.. - Örs, Batina.. (Correct)
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Y. S. Kim, W. S. Kang, and J. R. Choi. Implementation of 1024-bit modular processor for RSA cryptosystem. In Proceedings of Asia-Pasific Conference on ASIC (AP-ASIC), Cheju Island, Korea, August 28-30 2000.
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