F. Vahid and D. Gajski, "Specification partitioning for system design," in Proc. Design Automation Conf., 1992, pp. 219--224.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....engineering(CAE) tools used for hardware and software design is currently at the structural level for hardware and the compiler level for software. Industry has just begun to release behavior synthesizers for computer hardware, but many problems still exist. Much research has been done [10], but more is still needed to solve these problems. There is also a need for the next level of research involving partitioningthe system level description into hardware and software as well. There are many ways of approaching this research and many tradeoffs to consider [9] 2] 11] 5] 1.1. ....

....codesign. The researchers have developed estimators for both software and hardware. Their software estimator is based on a generic processor model method of estimation [4] Their hardware estimators can estimate based on many models such as a pin model, an area model, and a performance model [10]. Through the use of a graphical interface and graphical representations of their estimations, hardware software codesign can be done in an interactive environment. 2.2. COMET Di#erences COMET uses the C and VHDL languages directly ( along with the rules file) to perform hardware software ....

F. Vahid and D. D. Gajski. Specification partitioning for system design. 29th ACM/IEEE Design Automation Conference, pages 219--224, June 1992.

....hard realtime rate monotonic scheduling based ASIC design allows several tasks to share the same hardware during their execution. Hardware software codesign has received a great deal of attention recently [Wol94] The most relevant system research subdomain is hardware software partitioning [Bar94, Ern93, Gup93, Vah92]. These algorithms try to identify parts of computations which should be implemented on programmable and ASIC platform so that an overall optimization function is maximized. However, they do not address use and influence of hard real time operating scheduling constrains and operating systems ....

F. Vahid, D.D. Gajski, "Specification Partitioning for System Design", 29th DAC, pp. 219-224., 1992.

....subsystem based on standard components. Notable exceptions to this rule are papers dealing with retargetable compilation (e.g. Theissinger et al. 91] or with a very abstract formulation of partitioning for co design (e.g. Kumar et al. 92] 93] Prakash and Parker [94] and Vahid and Gajski [95]) The structure of the application specific hardware components, on the other hand, is generally much less constrained. Often, the communication mechanisms are also standardized for a given methodology. Few choices, often closely tied to the communication mechanism used at the specification ....

.... (outer) synthesis and similarity (HW) simulated annealing (inner) communication cost Olokutun [98] HDL task profiling (SW) Kernighan and Lin synthesis (HW) Kumar [93] set based task profiling mathematical programming Hu [99] task list task profiling branch and bound schedule analysis Vahid [95] acyclic DFG operation profiling (SW) mixed integer linear programming processor cost (HW) communication cost Barros (1) 100] Unity (HDL) operation similarity clustering concurruency sequencing Barros (2) 101] Occam operation similarity clustering hierarchy concurrenency sequencing ....

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F. Vahid and D. G. Gajski, "Specification partitioning for system design," in Proc. of the Design Automation Conf., June 1992.

.... synthesis benchmarks [Gebotys 1992] Highlevel synthesis group at the University of Southern California proposed several partitioning techniques for both high level synthesis [Kucukcaka and Parker, 1991] and system level synthesis [Prakash and Parker 1991] and at University of California, Irvine [Vahid and Gajski 1992] [Rao and Kurdahi 1992] Recently synthesis of application specific programmable processors (ASPP) Breternitz and Shen 1990] Guerra et al. 1993] and application specific instruction sets processors (ASIP) Leupers et al. 1994] Paulin et al. 1994] Goossens et al. 1995] received a great deal of ....

Vahid, F. and Gajski, D.D. 1992. "Specification Partitioning for System Design", 29th DAC, 219-224.

.... require a variable granularity size of the elements used during the high level transformation and synthesis steps to better utilize the architecture components (AC) In previous approaches, the size of these function elements ranges from processes in the input language [1] down to functions [12] and basic blocks or elementary threads [5, 6, 8] in ASIP design even down to individual statements [13] The optimization potential for a system scheduling and allocation process (for brevity, we will call it mapping process) rises with finer granularity (small elements) but the larger design ....

F. Vahid and D. D. Gajski, "Specification Partitioning for System Design", in Proc. of the 29 th Design Automation Conference, pp. 219--224, Anaheim, USA, 1992.

....input description. An important parameter in hardware software co synthesis is the granularity in partitioning, allocation, and scheduling, i.e. the size of the elements used in co synthesis. The size of these function elements ranges from processes in the input language [1] down to functions [11] and basic blocks or elementary threads [5, 6, 8] in ASIP design even down to individual statements [12] The size of these function elements defines the granularity. The optimization potential for system level scheduling and allocation rises with finer granularity (small elements) but the ....

F. Vahid and D. D. Gajski, "Specification Partitioning for System Design", in Proc. of the 29 th Design Automation Conference, pp. 219--224, Anaheim, USA, 1992.

....proliferates which will have a negative impact on the run time of scheduling and allocation and it may limit the system size or it may require the use of simpler heuristics. In previous approaches, the size of these segments ranges from processes in the input language [1] down to functions [16] and basic blocks or elementary threads [7, 9, 11] in ASIP design even down to individual statements [17] Work which is related to the work presented here can be found in the HW SW codesign domain. However, those approaches do not consider overlapping functionality. The advantages of ....

F. Vahid and D. D. Gajski, "Specification Partitioning for System Design", in Proc. of the 29 th Design Automation Conference, pp. 219--224, Anaheim, USA, 1992.

....on standard components. Notable exceptions to this rule are papers dealing with retargetable compilation (e.g. Theissinger et al. TSV94] or with a very abstract formulation of partitioning for co design (e.g. Kumar et al. KAJW92, KAJW93] Prakash and Parker [PP91] and Vahid and Gajski [VG92] The structure of the application specific hardware components, on the other hand, is generally much less constrained. Often, the communication mechanisms are also standardized for a given methodology. Few choices, often closely tied to the communication mechanism used at the specification ....

....hand (outer) synthesis and sim. anneal. similarity (HW) inner) communication cost Olokutun [OHLR94] HDL task profiling (SW) Kernighan synthesis (HW) and Lin Kumar [KAJW93] set based task profiling math. prog. Hu [HDMT94] task list task profiling branch sched. analysis and bound Vahid [VG92] acyclic DFG operation profiling (SW) Mixed processor cost (HW) Integer Linear communication cost Prog. Barros (1) BRX93] Unity (HDL) operation similarity clustering concurr. sequenc. Barros (2) BS94] Occam operation similarity clustering hierarchy concurr. sequenc. hierarchy Kalavade ....

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F. Vahid and D. G. Gajski. Specification partitioning for system design. In Proceedings of the Design Automation Conference, June 1992.

....process very time consuming; and (5) Power estimation measurement for rtl designs is too time consuming and not viable for very large designs. Recent efforts in system level synthesis have led to the development of high level synthesis systems that can produce multichip digital systems [4, 5, 6]. These systems, however, do not consider the impact of packaging on high level synthesis and hence designs produced by these systems cannot efficiently use available high performance packaging technology. For very large, performance critical designs, an efficient hierarchical behavioral ....

F. Vahid and D.D. Gajski, "Specification Partitioning for System Design," Proc. 29th Design Automation Conference, pp. 219--224, June 1992.

....and communication [25] These two concepts have brought new problems konwn as partitionning and communication synthesis. The goal of partitioning is to distribute a system functionality over a set of subsystems where each subsystem is to be executed either in software or in hardware processors [33]. The problem of communication synthesis [2] which appears after system level partitioning, is to fix the protocols and interfaces needed by the different susbsystems for the communication. A. Objective When designing distributed embedded systems, communication synthesis becomes essential as ....

F. Vahid, and D. Gajski, Specification Partitioning For System Design, Proceedings of the IEEE Design Automation Conference, pp. 219-224, June 1992.

....[1] The approach in [12] belongs to the same category, however, with extensions to allow for operations with non deterministic execution times. Tightly coupled with the class of input specifications is the scope of target architectures: ffl Dedicated control data path in VLSI: 19] 18] [25] are approaches to partition a functional specification for high level synthesis. The target architecture is in most cases a dedicated hardware architecture including a control path and a data path. ffl Multi chip dedicated VLSI architecture: Some methodologies do focus on multichip VLSI ....

....approaches can be classified according to their optimization model and procedure: Most of these mentioned methodologies consider system level synthesis as a partitioning problem. Partitioning techniques have been applied for many different problems in hardware synthesis, e.g. 5] 19] 18] [25]. There, the goal is in most cases to meet chip capacity and time constraints. Most of these approaches present a clustering based approach. In [17] multichip modules are considered, however no programmable components are allowed. In some clustering based approaches like [1] only the space ....

F. Vahid and D. Gajski. Specification partitioning for system design. In Proc. 29th Design Automation Conference, pages 219--224, Anaheim, CA, June 1992.

....to the same category, however, with extensions to allow for operations with non deterministic delays. Tightly coupled with the class of input specifications is the scope of target architectures: ffl Dedicated control data path in VLSI: McFarland, 1986 ] Lagnese and Thomas, 1991 ] Vahid and Gajski, 1992 ] are approaches to partition a functional specification for high level synthesis. The target architecture is in most cases a dedicated hardware architecture including a control path and a data path. ffl Multi chip dedicated VLSI architecture: Some methodologies do focus on multichip VLSI ....

....and procedure: Most of these mentioned methodologies consider system level synthesis as a partitioning problem. Partitioning techniques have been applied for many different problems in hardware synthesis, e.g. Camposano and Brayton, 1987 ] McFarland, 1986 ] Lagnese and Thomas, 1991 ] Vahid and Gajski, 1992 ] There, the goal is in most cases to meet chip capacity and time constraints. Most of these approaches present a clustering based approach. Ku cuk cakar and Parker, 1995 ] considers multichip modules, however no programmable components are allowed. In some clustering based approaches like ....

F. Vahid and D. Gajski. Specification partitioning for system design. In Proc. 29th Design Automation Conference, pages 219--224, Anaheim, CA, June 1992.

....into processes are also shown. The processes created using their method have a very simple interaction scheme to transfer data values and control signals using message passing. Their approach can not synthesize components using complex protocols for data transfers and synchronization. SpecPart [9] partitions algorithm process grained computations from the SpecChart behavioral specifications. Default protocols are used for interaction between components. The CHOP systemlevel design partitioner [10] uses task graphs to specify the protocol between every partition. Special purpose hardware ....

F. Vahid and D. D. Gajski, "Specification partitioning for system design," in Proceedings of the 29th ACM/IEEE Design Automation Conference, pp. 219--224, 1992.

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F. Vahid and D. Gajski, "Specification partitioning for system design," in Proc. Design Automation Conf., 1992, pp. 219--224.

....quality of alternative solutions. Once a satisfactory design is found, the original system specification is refined into a set of module specifications. To further reduce the workload of the designer, the tasks of module allocation, partitioning, and refinement can be automated by various tools [12, 13, 14]. Once the system modules have been completely specified as a result of system design tasks, we can use software generators and hardware design compilers [15, 16] to obtain a software hardware implementation of each module. By capturing desired functionality with an executable specification ....

F. Vahid and D. Gajski, "Specification Partitioning for System Design," in Proceedings of the Design Automation Conference, 1992. 46

....While simulation of the generated VHDL is slower, it is not by an order of magnitude which might then require a SpecCharts simulator. SpecCharts is currently being used as the input language (along with VHDL) to a set of systemdesign tools which we are implementing, including a partitioner [20], estimators [21] and an interface synthesis tool. It has also been used in an industry design of a controller in which the behavior was specified in SpecCharts, which was then manually translated to C and then compiled for execution on a microcontroller. The designer estimated a 20 reduction in ....

F. Vahid and D. Gajski, "Specification Partitioning for System Design," in Proceedings of the Design Automation Conference, 1992.

....heuristics employed. Clustering heuristics are used in [14] and [15] integer linear programming in [16] and [17] manual partitioning in [18] and iterative improvement heuristics in [19] and [20] Other techniques for hardware partitioning operate at a higher level of granularity, such as in [21] where processes and subroutines are partitioned among ASIC s using clustering, iterative improvement, and manual techniques. Experiments have shown tremendous advantages of functional partitioning over the current practice of structural partitioning [22] Hardware software partitioning ....

F. Vahid and D. Gajski, "Specification partitioning for system design," in Proc. Design Automation Conf., 1992, pp. 219--224.

....parameters needed by a hardware size estimator. As we shall see, we were able to do this by assuming that the granularity at which we partition the specification is at the procedural level (sometimes called the process or task level) as is the case in many new functional partitioning techniques [7, 8, 10, 11, 12, 13, 14, 15]. Our contribution is the development of this incremental hardware size estimation method, consisting of a new data structure and algorithm, that achieves the advantages of both classes of previous approaches, namely accuracy and speed. This paper is organized as follows. In Section 2, we describe ....

....the first three examples consisted of one process, while the Ethernet coprocessor example contained 14 processes. For each example, we first measured the time to build the preprocessed information. We then applied the group migration algorithm [17] using the cost function specified in [10]. Shown in the table are the number of moves that the algorithm examined, and the CPU time (in seconds on a Sparc1) required to update the estimation information and obtain a new hardware size estimate for each move. Note that the time per move is roughly the same across all four examples, ....

F. Vahid and D.Gajski, "Specification partitioning for system design," in Proceedings of the Design Automation Conference, pp. 219--224, 1992.

....of closeness metric definition. In [5] and [15] arithmetic level operations are partitioned among ASICs using iterative improvement algorithms. In [16] and [17] specification pieces are partitioned among a simple hardware software architecture, again using iterative improvement algorithms. In [18] and [19] processes and procedures of a specification are partitioned among ASICs using iterative improvement or genetic algorithms. In [20] and [21] ILP formulations are presented for simultaneously scheduling arithmetic operations and partitioning them among ASICs. In [22] an ILP formulation ....

F. Vahid and D. Gajski, "Specification partitioning for system design," in Proceedings of the Design Automation Conference, 1992.

....(CutBuses(p) which in turn are those buses that implement at least one channel crossing the boundary. 4 Related work Many projects focus on partitioning functionality among hardware or hardware software components. The need for coarse grained procedural level partitioning was stressed in [2], as well as in [3, 4] Approaches in [5, 6, 7] partition at the finer grained statement level (or statement sequence) Other approaches, such as those in [8, 9, 10, 11, 12, 13] partition at the fine grained arithmetic operation level. Additional research has focused on functional ....

F. Vahid and D.Gajski, "Specification partitioning for system design," in DAC, pp. 219--224, 1992.

....functions are implemented as structure. The existence of functional specifications means that such functional partitioning can now be automated. In fact, several research efforts have addressed such automation, hypothesizing that functional partitioning would excel over structural partitioning [10, 11, 12, 13, 14]. This paper provides empirical results for the hypothesis that: Functionally partitioning a specification results in better satisfaction of hardwarepart size and I O constraints, and often yields better design performance, than achievable through structural partitioning. For example, consider ....

....YSC uses a hierarchical clustering algorithm to form clusters, with a closeness threshold used to terminate clustering. Results showed greatly reduce logic synthesis times when synthesizing each of the clusters separately, as compared with synthesizing the entire behavior. 2. 7 SpecSyn SpecSyn [34, 14] is a partitioner at the procedure level. SpecSyn considers three design metrics: area, I O pins, and performance. It converts the input processes or program state machines into SLIF [35] format, resembling a call graph where the nodes are procedures and variables and edges represent accesses. The ....

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F. Vahid and D.Gajski, "Specification partitioning for system design," in Proceedings of the Design Automation Conference, pp. 219--224, 1992.

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F. Vahid, and D. Gajski, Specification Partitioning For System Design, Proceedings of the IEEE Design Automation Conference, pp. 219-224, June 1992.

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F. Vahid and D. D. Gajski, "Specification partitioning for system design," in Proc. Design Automation Conf., pp. 219-224, June 1992.

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F. Vahid, D.D. Gajski. Specification Partitioning for System Design. In proceedings of the 29th Design Automation Conference, pages 219-224. AnaheimCalifornia, 1992.

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F. Vahid and D. D. Gajski, "Specification Partitioning for System Design," Proceedings of the Design Automation Conference (DAC), pp. 219-224, June 1992.

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