J. A. Nestor and V. Tamas. Exploiting scheduling freedom in controller synthesis. In Proc. of the Int'l Workshop on High-Level Synthesis, pages 74--86, November 1992. Home/Search Document Details and Download
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Multi-Layer Intermediate Representation for ASIP Design.. - Dittmann, Herkersdorf (2003) (Correct)
....control edges. This is represented by a multiplexer consisting of one box per arriving control edge. Each box joins a control edge with the meta DFG edges it requires. Finally, a way of representing time dependencies are output transition graphs (OTGs) as introduced for controller FSMs in ASICs [12], where edges are annotated with the minimum and maximum time between nodes and scheduled nodes are annotated with the determined time step, given for instance in processor cycles. We combine DFG, Petri net, meta DFG, and OTG into a multi layer IR with a single start node and a single end node. ....
J. A. Nestor and V. Tamas. Exploiting scheduling freedom in controller synthesis. In Proc. of the Int'l Workshop on High-Level Synthesis, pages 74--86, November 1992.
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