Donald E. Thomas and Philip R. Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 3rd edition, 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....description languages focus on describing systems in the behavioral and structural domains. However, due to their origin as languages for hardware design, they frequently do not include strong capabilities for abstracting over data and for describing complex interactions. For example, in Verilog [12, 18], data types are closely bound to their binary representation, and signalling between modules includes aspects of electrical implementation. VHDL [1, 11] on the other hand, allows more abstract expression of data, and its type system is similar to that of conventional programming languages. ....

D. E. Thomas and P. R. Moorby, The Verilog Hardware Description Language, Third ed. Boston, MA: Kluwer Academic Publishers, 1996.

....[4] and early versions of Simulink [49] are based on these models. Discrete event models have a global notion of time and time stamped events. They are suitable for modeling timing properties in digital circuits, network traffic, and queuing systems. Languages and tools like VHDL [44] Verilog [46], and ns [6] are primarily based on these models. In some discrete event models, the time stamps of all events are multiples of a predefined time interval. These discretetime models are used in discrete control systems and cycleaccurate simulations. In many system modeling methodologies, time is ....

D. E. Thomas and Philip Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, USA, 1991.

....of processes. Informally, LTSs are similar to state transition diagrams where the transition between the states are labelled by events that occur in the environment. We shall use LTSs as our models of F and D. LTSs are formally defined in chapter 3. Many high level specification languages [49, 35, 20, 8, 16, 29] can be used to model reactive systems such as embedded systems. In this paper, we selected LTSs rather than any of these languages to model F and D since LTSs have often been used as the underlying semantics of many of these languages and they often might compile to LTSs or automata as in the ....

....automatically. However this approach did not handle data width mismatches between the two incompatible hardware. This limitation was overcome in later work by Narayan and Gajski [34] In this work the be haviours of the two incompatible blocks were represented in a hardware description language [49, 20] and then the algorithm verified if the two protocols were duals of each other. If they were not exact duals of each other then necessary extra control signals on either side were appropriately generated and the data width mismatches were also bridged by latching data values within local memory of ....

D. E. Thomas and P. Moorby. The Verilog Hardware Description Language. Kluwer Academic, 1991.

....of modeling reactive hardware systems. Indeed, most existing HDLs can be classified as source languages for a corresponding event driven simulator [34] An event driven model is powerful enough to describe most hardware systems at any level of abstraction: from algorithms to gate level circuits [61]. However, this generality also imposes a significant burden on the simulation efficiency due to the extra work (or overhead) needed in event maintenance and processing. Event processing often requires interpretation of event generation, propagation and disposition by the simulation model. ....

Thomas, D., and Moorby, P. The Verilog Hardware Description Language. Kluwer Academic Publishers, 1996.

....is still based on simulation. Some simulationbased verification approaches have been presented in the literature [4, 5, 6] They usually compare the specification and the implementation of a device described by means of a hardware description language (HDL) such as VHDL [7] or Verilog [8]. Such techniques differ in the way the functional test patterns are identified since test patterns application to both specification and implementation and results comparison can be performed by using standard HDL simulators. Whenever production testing is approached, test patterns are computed ....

D.E. Thomas, P. Moorby. The Verilog Hardware Description Language. Kluwer Academic Publisher, Nowell Massachusetts, 1991.

....versions of Simulink (by The MathWorks) are based on these models. Discrete event models have a global notion of time and timestamped events. They are suitable for modeling timing properties in digital circuits, network traffic, and queuing systems. Languages and tools like VHDL [41] Verilog [45], and ns [10] are primarily based on these models. In some discrete event models, the time stamps of all events are multiples of a predefined time interval. These discrete time models are used in discrete control systems and cycle accurate simulations. In many system modeling methodologies, time ....

D. E. Thomas and Philip Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, USA, 1991.

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D. E. Thomas and P. R. Moorby, The Verilog Hardware Description Language. Boston, MA: Kluwer Academic, 1991.

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D. E. Thomas and P. R. Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 3rd edition, 1996.

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D.E. Thomas, and P.R. Moorby, The Verilog Hardware Description Language, 4th edition, Kluwer Academic Publishers, Boston/Dordrecht/London, 1998.

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P. Moorby, D. Thomas, "The Verilog Hardware Description language", Kluwer Academic Publishers, 2002.

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D. E. Thomas and P. R. Moorby. The Verilog hardware description language. Kluwer Academic Publishing, Boston, MA, 1991.

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D. Thomas and P. Moorby. The Verilog Hardware Description Language. Kluwer Academic Publishers, 2. edition, 1995.

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