J. Noguera and R. Badia. A HW/SW partitioning algorithm for dynamically reconfigurable architectures. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'2001. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
A Framework for System-Level Partitioning of.. - Schulz-Key, Kuhn.. (2001) Self-citation (Partitioning) (Correct)
No context found.
J. Noguera and R. Badia. A HW/SW partitioning algorithm for dynamically reconfigurable architectures. In Proceedings of the Design, Automation and Test in Europe Conference (DATE'2001.
Dynamic Run-Time HW/SW SchedulingTechniques for.. - Noguera, Badia (2002) Self-citation (Noguera Badia) (Correct)
....states (e.g. execution, reconfiguration, etc. We also define the functional unit active set to include the following information: functional unit state, TaskId, TaskType and TaskGraph, of the task being processed in the functional unit. 3.2. Codesign Methodology The proposed methodology [11][12] is divided into three stages: Application Stage, Static Stage and Dynamic Stage. The application stage is focused on the system specification. The static stage includes: 1) extraction, 2) estimation, 3) HW SW partitioning, and (4) HW and SW synthesis. The extraction phase has two main ....
....(e.g. delay and area) that can be obtained using high level synthesis and profiling tools. The HW SW partitioning phase decides which task types will be executed in reconfigurable HW and which in SW. HW SW partitioning has been demonstrated to be a critical point when targeting DRL architectures [12]. The dynamic scheduling results highly depend on the quality of the HW SW partitioning, which helps to reduce the run time reconfiguration overhead. The dynamic stage includes HW SW Scheduling and DRL MultiContext Scheduling. Both of them run in parallel and base their functionality on events ....
[Article contains additional citation context not shown here]
J. Noguera, R. M. Badia, "A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures", Proc. of DATE'2001
Reconfigurable SoC Design with Hierarchical FSM and.. - Lee, Yoo, Choi (2002) (Correct)
No context found.
J. Noguera and R. M. Badia, "A HW/SW Partitioning Algorithm for Dynamically Reconfigurable Architectures", Proc. Design Automation and Test in Europe, pp. 72934, 200t.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC