P. J. Hanlon, D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, , and E. Parker. The combinatorics of cache misses during matrix multiplication. 2000. to appear in the Journal of Computer Sciences and Systems. Home/Search Document Details and Download
Summary Related Articles |
This paper is cited in the following contexts:
Is Morton layout competitive for large Two-Dimensional Arrays - Thiyagalingam, Kelly (2002) (Correct)
....traversal. In fact, this applies given any cache hierarchy with even power of two block size at each level. This is illustrated in Fig. 1. The problem of calculating the actual cache performance with Morton layout is somewhat involved; an interesting analysis for matrix multiply is presented in [6]. void mm ikj tb(double A[SZ SZ] double B[SZ SZ] double C[SZ SZ] unsigned int MortonTabEven[ unsigned int MortonTabOdd[ int i, j, k; double r; for (i = 0; i SZ; i ) for (k = 0; k SZ; k ) r = A[MortonTabEven[i] MortonTabOdd[k] for (j = 0; j SZ; j ) ....
P. J. Hanlon, D. Chung, S. Chatterjee, D. Genius, A. R. Lebeck, , and E. Parker. The combinatorics of cache misses during matrix multiplication. 2000. to appear in the Journal of Computer Sciences and Systems.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC