| Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, , and Anant Agarwal. Bearing it all to software: RAW machines. Computer, pages 86--93, September 1997. |
....lane are increased [11] However, to our knowledge, no previously published studies explore VLSI costs or performance as vector microprocessors are scaled to greater than 8 or 16 vector lanes. Other related work includes approaches where stream programs are mapped to on chip processor arrays [3, 12, 21] and investigations into the impact of technology scaling on general purpose microprocessors [1] 3. VLSI Cost Models Not only do stream processors naturally exploit the parallelism and locality in media applications, but they are also area and energy efficient, primarily due to their register ....
E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Bearing it all to software: RAW machines. IEEE Computer, pages 86--93, September 1997.
No context found.
Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, , and Anant Agarwal. Bearing it all to software: RAW machines. Computer, pages 86--93, September 1997.
No context found.
Elliot Waingold, Michael Taylor, Devabhaktuni Srikrishna, Vivek Sarkar, Walter Lee, Victor Lee, Jang Kim, Matthew Frank, Peter Finch, Rajeev Barua, Jonathan Babb, Saman Amarasinghe, , and Anant Agarwal. Bearing it all to software: RAW machines. Computer, pages 86--93, September 1997.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC