H. Savoj. Don't Cares in Multi-Level Network Optimization. Ph.D. dissertation, UC Berkeley, May 1992.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....computation, a logic node and its fanins are optimized simultaneously. When the fanins of a node F are modified, the logic function of F needs to be changed as well. In [5] to avoid the propagation of changes throughout the transitive fanout of F , the CODCs (compatible output don t cares) [7] of the immediate fanouts of F are used to block the changes of F . For the application of MV SPFDs in PLA based wire removal, the changes to any node (i.e. a PLA) F do not need to be blocked by the don t cares of nodes in the fanout of F . This is because fanout PLAs can be easily re implemented ....

H. Savoj, Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....the wire g does not do anything and can be removed. If we now alter the functions of nodes g and z 1 to reflect these changes (for details on how to do this, see [14] the new simplified circuit can be represented as: The additional flexibility that (MV )SPFDs provide over CODCs [11] or redundancy removal is due to the fact that we alter the function of each node and its fanins simultaneously. This allows minterms in the original onset and offset to be suitably swapped to get many different functions, some of which cannot be obtained by CODCs or redundancy removal. Note that ....

....0 A 0 A 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 Table 1. Function Table of PLA A B 0 B 1 B 2 C 0 A 1 3 0 0 0 0 1 1 1 1 0 2 Table 2. Function Table of MV node h A this can prove to be expensive. So we block the changes in the new function by its MV CODCs [6] a generalization of CODCs [11] for the multi valued case) In other words, we only consider those changes at P which would be contained in its MV CODC set. Thus, at any point in the algorithm, the region of change consists of a single node, and possibly its immediate fanins. Let us consider the following simple example to ....

H. Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....and XDCs. Once the SDCs are computed and the XDCs and CODCs are expressed in terms of immediate fanins, a two level minimization algorithm is invoked to find an optimized expression. This is simply a brief description of the full simplify. For a more detail explanation, we refer the readers to [6]. Lemma 7 Throughout full simplify computation, the only steps that can introduce illegality into the network are the image computation and the SDC computation. Proof: Let node n be the node we are computing don t cares for. Legality of the Boolean network can only change if an edge is added to ....

H. Savoj. Don't cares in multi-level network optimization. PhD thesis, University of California, Berkeley, May 1992.

....i , x j , f ( x j , x i , Shannon s form of individual variable swaps represents a subset of all generators and thus can represent only a subset of the symmetries. For the above given example these symmetries are described by GP = 2,1,3,4) 1,2,4,3) In [10, 18, 19], the concept of functional symmetry is extended to include swaps between groups of inputs. Kravets and Sakallah [9] give another generalization by introducing higherorder symmetries based on hierarchical swaps of sets of inputs. The authors also consider functional symmetry under input ....

H. Savoj, Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California, Berkeley, CA, 1992.

.... structure (which is the topic of this paper) consequently, one is chosen according to some optimality criteria (e.g. minimum state [15] For combinational designs, the problem of determining and using the flexibility afforded by don t care conditions is well solved both in theory and practice [28]. We propose the use of the logic S1S as a mathematical framework for studying the synthesis of sequential designs. We will show that this leads to simple and mathematically elegant solutions to problems arising in the synthesis and optimization of synchronous digital hardware. Specifically, we ....

H. Savoj, "Don't Cares in Multi-Level Network Optimization," PhD thesis, The University of California at Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA, May 1992.

....selected. A preorder traversal is recursively called at the g s gate inputs. 2.3 Don t Care Computation for Area Optimization One advantage of the Boolean covering is the ability to extend the matching possibilities by using the network don t cares. Mailhot (Ceres environment [MM93] and Savoj [Sav92] proposed two main approaches to the Boolean covering problem with don t cares. In Ceres, the matching don t care handling was implemented with compatible graphs. The drawback is that the size of these graphs is exponential in the number of input variables, and their application is thus limited to ....

....is exponential in the number of input variables, and their application is thus limited to functions with a maximum of four inputs. In the covering step, Ceres uses only controllability don t care sets that are computed dynamically as the mapping operation proceeds through the network. Savoj [Sav92] presented a Boolean matching method based on the tautology check. The main problem in this approach is to find the initial variable permutation . Savoj introduced a class of filters for the matching with don t care conditions (commonly named DC) In the covering step, the network is first ....

Hamid Savoj. Don't Care in Multi-level Network Optimization. PhD thesis, University of California, Berkeley, California, 1992.

....output phase assignment was proposed by Mailhot [3] This algorithm uses compatible graphs to solve this problem. The drawbackis that the size of these graphs is exponential in the number of inputs variables, and their application is thus limited to functions with a maximum of four inputs. Savoj [7] presented a method based on the tautology check. The main problem in this approach is to find the variable assignment. Savoj introduced a class of filters that are valid even for incompletely specified functions. Lastly, a new approach, using multi valued functions, was presented byWang [9] in ....

....permutation must be found. The controlling value approach developed here was implemented and integrated with a Boolean mapper, called Land, in the SIS environment. The implementation includes a Boolean covering (cluster generation) and uses standard signatures techniques and symmetrical prune [7], 8] The results of Land on some benchmark examples for the 1991 International Workshop on Logic Synthesis are presented in table 1. The library used is example.genlib,which come with the SIS distribution. The column gates gives the number of gates, the column area gives the area of mapped ....

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H. Savoj. "Don't Care in Multi-level Network Optimization, " PhD thesis, University of California, Berkeley,1992.

....the simple logic using existing logic optimization techniques. In particular, the notion of don t cares sets, i.e. inputs for which a gate can output any value carries over from logic synthesis on simple combinational networks [10] the same is true of compatible sets of permissible functions [4, 11] is useful. The latter correspond to subsets of the complete set of don t cares for individual gates with the property that gates can be independently simplified with respect to these subsets, without requiring that don t cares to be recomputed. Definition 3 Let D be a complex combinational ....

....simplifying gate G in D, the don t cares for other gates may have changed. Thus it is necessary to recompute the don t cares for the remaining gates, which is potentially expensive computationally. Almost the same degree of optimization can be achieved using the concept of compatible don t cares [4, 11]. These don t cares can be used independently to optimize the gates; they too can be directly computed from the network D CHECKER . 4.3 Experiments In this section we report experimental results on the synthesis of complex combinational netlists; these experiments were performed in the SIS ....

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Hamid Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

.... using some finite structure and then one is chosen according to some optimality criteria (e.g. minimum state [12] For both combinational and sequential designs, the problem of determining and using the flexibility afforded by don t care conditions is well solved in both theory and practise [16, 7, 21]. 1 DAC 1997 Submission Optimizing Designs Containing Black Boxes 2 In this paper we describe algorithms for synthesizing gate level hardware designs which contain black boxes , i.e. components whose functionality is not to be used. These can arise in many ways: 1. In hierarchical ....

....the simple logic using existing logic optimization techniques. In particular, the notion of don t cares sets, i.e. inputs for which a gate can output any value carries over from logic synthesis on simple combinational networks [15] the same is true of compatible sets of permissible functions [7, 16] is useful. The DAC 1997 Submission Optimizing Designs Containing Black Boxes 15 latter correspond to subsets of the complete set of don t cares for individual gates with the property that gates can be independently simplified with respect to these subsets, without requiring that don t cares to ....

[Article contains additional citation context not shown here]

Hamid Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

.... using some finite structure and then one is chosen according to some optimality criteria (e.g. minimum state [12] For both combinational and sequential designs, the problem of determining and using the flexibility afforded by don t care conditions is well solved in both theory and practise [16, 7, 21]. DAC 1997 Submission Optimizing Designs Containing Black Boxes 2 In this paper we describe algorithms for synthesizing gate level hardware designs which contain black boxes , i.e. components whose functionality is not to be used. These can arise in many ways: 1. In hierarchical synthesis, ....

....the simple logic using existing logic optimization techniques. In particular, the notion of don t cares sets, i.e. inputs for which a gate can output any value carries over from logic synthesis on simple combinational networks [15] the same is true of compatible sets of permissible functions [7, 16] is useful. The latter correspond to subsets of the complete set of don t cares for individual gates with the property that gates can be independently simplified with respect to these subsets, without requiring that don t cares to be recomputed. Definition 7 Let D be a complex combinational ....

[Article contains additional citation context not shown here]

Hamid Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....functions. Here, flexibility means choice in the actual function implemented (as opposed to choice in how that function is implemented) Flexibility in various forms has been studied extensively, and includes don t care conditions for optimization of combinational [BHMSV84, BBH 88, MKLC89, Sav92] and sequential [DM92a, RHS91] two level and multi level circuits as single entities (each output can be optimized independently) Boolean relations [BS89b, BS89a, WB91] which express relationships between outputs and are derived from the surrounding environment, and synchronous recurrence ....

....environment of interacting finite state machines, the observability and the controllability of a finite state machine is reduced. This sequential flexibility is referred to as sequential controllability and observability don t cares, quite similar to the case for combinational circuits [Sav92] As [RHS91] have shown, the sequential don t cares for the interacting finite state machine environment can be represented as finite sequences of input output pairs. This can be naturally cast into the synchronous recurrence equations that we discussed in the last section. We can then use the ....

Hamid Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

.... structure (which is the topic of this paper) and then one is chosen according to some optimality criteria (e.g. minimum state [23] For combinational designs, the problem of determining and using the flexibility afforded by don t care conditions is well solved in both theory and practise [37]. Using the logic S1S as our basic tool we show that the set of all implementations can always be captured by a single finite state automaton, which can be generated automatically. However, in practice such an automaton may be prohibitively large to construct; we define define automata which ....

Hamid Savoj. Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....and iterate until convergence. Our goal to learn all compatible implications in the circuit in one step and use the compatibility of these implications to remove all the redundancies simultaneously (in this sense our method for finding compatible unobservabilities is related to the work in [2, 3] for computing compatible ODC s (observability don t cares) This is our first contribution. Secondly, we generalise the implication procedure by combining it with recursive learning [4] to enhance the capability of the redundancy identification procedure. Recursive learning lets us perform case ....

H. Savoj, Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....on heuristic Boolean minimization. Since we are recomputing a new O R new (v; u) many times during the iterative algorithm, it becomes pertinent to explore incremental ways of updating the relation, rather than recomputing it from the beginning. We expect that some of the methods adapted from [83] may be used. 151 Chapter 8 Conclusions and Future Work The main contributions of this thesis have been: 1. To motivate the need for incremental algorithms in CAD; in particular logic synthesis and formal verification. 2. To provide a theoretical framework for the construction of such ....

H. Savoj, Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

....on heuristic boolean minimization. Since we are recomputing a new O R new (v; u) many times during the iterative algorithm, it becomes pertinent to explore incremental ways of updating the relation, rather than re computing it from the beginning. We expect that some of the methods adapted from [11] may be used. ....

H. Savoj, Don't Cares in Multi-Level Network Optimization. PhD thesis, University of California Berkeley, Electronics Research Laboratory, College of Engineering, University of California, Berkeley, CA 94720, May 1992.

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H. Savoj. Don't Cares in Multi-Level Network Optimization. Ph.D. dissertation, UC Berkeley, May 1992.

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H. Savoj, "Don't cares in multi-level network optimization," Ph.D. dissertation, UC Berkeley, May 1992.

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H. Savoj. Don't Cares in Multi-Level Network Optimization. Ph.D. thesis, UC Berkeley, 1992.

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H. Savoj. Don't Cares in Multi-Level Network Optimization. Ph.D. dissertation, UC Berkeley, May 1992.

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