D. Brand, A. Drumm, S. Kundu, and P. Narain, "Incremental synthesis," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 14--18.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....of control and observation logic with this fine granularity. Therefore, back end CAD tool effort is minimized for debugging changes. Other techniques have been developed to minimize logic resynthesis [12] and restrict synthesis to modified portions of the design after an engineering change [1], reducing the front end CAD effort. Similarly, lower level design perturbation due to high level engineering changes has been limited by another methodology [4] thus helping to minimize the number of affected 208 tiles at the physical level. Employing these time and effort reduction front end ....

Brand, D. et al., "Incremental synthesis," thternational Conference on Cornputer-A ided Design, 1994, 14-18.

.... Further, an efficient verification method for such cases is also an important integral part if modifying and updating a given design shall become an automated process (incremental synthesis) Approaches to incremental synthesis and automatic design error corrections have been reported in [6, 12, 18]. Logic verification belongs to the most difficult problems in the field of computer aided circuit design. Even verification of small designs can lead to enormous computation times, requiring large amounts of memory. The difficulty of the logic verification problem arises from having to explore ....

Brand D. et al.: " Incremental Synthesis", IEEE International Conference on Computer-Aided Design (ICCAD), Nov. 1994, Santa Jose, pp. 14 - 18.

....procedure is applied. This is undesirable, as it can jeopardize some of the engineering effort already invested in the design. In the problem of engineering change, one is interested in the least amount of resynthesis on the existing design to obtain one that satisfies the new specification [5], 11] 12] 17] Depending upon the information available, two versions for engineering change can arise. For each version, a fundamentally different solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old ....

....engineering change can arise. For each version, a fundamentally different solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old specification and the existing design is available from the synthesis process. Existing work [5], 11] 12] uses this information to resynthesize the signals that are not functionally equivalent. In the second version [17] such a naming correspondence is not available as the old and new specification can only provide primary output responses in terms of the primary input stimuli. It is ....

D. Brand, A. Drumm, S. Kundu, and P. Narain, "Incremental synthesis," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design, 1994, pp. 14-18.

....not belong to any type in the model, then no solution can be produced. Engineering change (EC) is a problem closely related to errorcorrection. Its goal is to reuse the existing investment on the implementation of a circuit when a specification is slightly changed. An EC algorithm was proposed in [7] assuming three netlists are given: the new specification, the old specification and the old implementation. This approach uses automatic test pattern generation (ATPG) techniques to identify equivalent signal pairs between the new specification and the old implementation, for the purpose of ....

....We sort the key signals in an order that every signal is after its transitive fanins. Once an equivalent signal pair (a 1 , a 2 ) is identified, a 1 is replaced by a 2 immediately. This incremental approach identifies equivalent pairs in stages to significantly reduce the run time complexity [7]. After we have checked every internal key signal pair, we check if the output functions o 1 and o 2 are equivalent. If they are equivalent, then no more correction is needed. Otherwise, we select an inequivalent pair and perform back substitution. After the back substitution, another iteration of ....

D. Brand, A. Drumm, S. Kundu, and P. Narrain, "Incremental Synthesis, " Proceedings of ICCAD, pp. 14-18, 1994.

....local or incremental change. Often these local changes are made to react to local change in the design, correct local errors or to make local improvements in one or more of the design quality metrics. Mechanisms are needed to control the portions of the design that are exposed for optimization [2]. And algorithms are needed to obtain good incremental solutions in a short amount of time. Many iterative algorithms such as simulated annealing, force directed algorithms, and maze routing can be easily modified to handle incremental floorplanning, placement, and routing. The main challenge is ....

....these algorithms to and what are the quality speed tradeoff. A small number of research results in the area of incremental layout have been reported in the recent past, focusing on floorplanning [12] placement [4] and FPGA routing [14, 43] Incremental logic optimization has been studied in [2, 50], and incremental FPGA technology mapping in [8] A major difficulty in physical design is the cycling dependency and strong interaction between placement, synthesis, and routing. To estimate the timing, one needs to know the interconnect, which requires a placement, which itself should be ....

D. Brand, A. Drumm, S. Mundu, and P. Narain. "Incremental Synthesis". In Proceedings of the International Conference on Computer-Aided Design, pages 14--18. IEEE, November 1994.

....procedure is applied. This is undesirable as it 25 can jeopardize some of the engineering e#ort already invested in the design. In the problem of Engineering Change, one is interested in the least amount of re synthesis on the existing design to obtain one that satisfies the new specification [5, 11, 12, 17]. Depending upon the information available, two versions for engineering change can arise. For each version, a fundamentally di#erent solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old specification and the existing ....

....engineering change can arise. For each version, a fundamentally di#erent solution is developed. In the first version, a naming equivalence (i.e. functional equivalence) between signals of the new and old specification and the existing design is available from the synthesis process. Existing work [5, 11, 12], uses this information to re synthesize the signals that are not functionally equivalent. In the second version [17] such a naming correspondence is not available as the old and new specification can only provide primary output responses in terms of the primary input stimuli. It is reported by ....

D. Brand, A. Drumm, S. Kundu and P. Narain, "Incremental Synthesis," in Proc. of the IEEE/ACM Int'l Conf. on Computer--Aided Design, pp. 14-18, 1994.

....In these cases, design error diagnosis and logic rectification is needed. Automatic error diagnosis and correction save a lot of design debugging time. Existing logic rectification approaches can be classified into several categories: error model based approaches [2 5] structural approaches [6 8], and re synthesis based approaches [911 ] In error model based approaches, after error diagnosis, the implementation is rectified by matching the error with an error type in the model. The method is relatively restricted because it may fail in error cases not covered by the model. In this ....

....the implementation is rectified by matching the error with an error type in the model. The method is relatively restricted because it may fail in error cases not covered by the model. In this approach, the case of multiple errors has not been investigated because of the problem complexity. In [6], a structural approach was proposed for engineering change [12] In engineering change, in order to re use the engineering effort spent on the old implementation, logic rectification is performed to realize the new specification by modifying the old implementation. This approach applies ....

D. Brand, A. Drumm, S. Kundu, P. Narrain. Incremental Synthesis. Proceedings of ICCAD, pp.14-18, 1994.

.... [Wat91, Kha96] Techniques for minimal alteration of an existing logic network focus on developing estimationbased iterative search techniques for minimal logic resynthesis [Swa97] or on reusing gates from the initial implementation and restricting synthesis only to the modified portions [Bra94]. Alternative wires, interconnects that can replace a target wire without changing circuit s functionality, have been shown to aid postlayout logic restructuring [Cha97] Fang et al. have developed an RT level EC method which establishes data relationships between design stages and localizes the ....

D. Brand, et al. Incremental synthesis. ICCAD, pp.14-18, 1994.

....(Section 4.3) and a greedy algorithm that works well in practice (Section 4.4) Section 5 describes the results of some experiments on the algorithms and presents our conclusions. 2 Previous Work Other approaches to incremental synthesis rely on knowing input correspondences. Brand et al. s [3, 4] work on incremental synthesis identifies regions of commonality similar to our own, but they require knowledge of input correspondences and can only detect regions that start at the inputs. Burch et al. 5] solve a functional matching problem that does not require input correspondence ....

D. Brand, A. Drumm, S. Kundu, and P. Narain, "Incremental Synthesis," in Proc. Intl. Conf. on Computer-Aided Design, pp. 14--18, Nov. 1994.

....(Section 4.3) and a greedy algorithm that works well in practice (Section 4.4) Section 5 describes the results of some experiments on the algorithms and presents our conclusions. 2 Previous Work Other approaches to incremental synthesis rely on knowing input correspondences. Brand et al. s [3, 4] work on incremental synthesis identifies regions of commonality similar to our own, but they require knowledge of input correspondences and can only detect regions that start at the inputs. Burch et al. 5] solve a functional matching problem that does not require input correspondence ....

D. Brand, "Incremental Synthesis," in Proc. Intl. Conf. on Computer-Aided Design, pp. 126--129, Nov. 1992.

....the network may have already been implemented in silicon at a lower level of the design hierarchy, and it can be inconvenient to change. Previous algorithms for the problem of incremental synthesis have dealt with post rectification (Watanabe et al. 9] and preserving conesof logic (Brand et al.[1]) in the design. Some relevant work has also been done by Kukimoto and Fujita [4] but this is concerned with FPGA s rather than general logic. In addition, this work restricted re synthesisizable parts of the network to all nodes at a level, rather than general re synthesis region. Other ....

D. Brand. Incremental Synthesis. In Proc. Intl. Conf. on Computer-Aided Design, pages 126--129, Nov. 1992.

....connectivity information to find nodes that have identical structures in their transitive fanins. Finally, the matchings implied by these nodes are combined into a high quality matching. We use both a greedy heuristic, as well as an exact formulation. It is not correct to compare Brand et al. s [1] work on incremental synthesis with this work, because they require knowledge of input correspondences and can only detect regions that start at the inputs and have the exact same function. Another relevant piece of work by Burch et al. [5] solves a functional matching problem that does not require ....

D. Brand, A. Drumm, S. Kundu, and P. Narain. Incremental Synthesis. In Proc. Intl. Conf. on Computer-Aided Design, pages 14--18, Nov. 1994.

....the network may have already been implemented in silicon at a lower level of the design hierarchy, and it can be inconvenient to change. Previous algorithms for the problem of incremental synthesis have dealt with post rectification (Watanabe et al. [34] and preserving cones of logic (Brand et al. [76]) in the design. Some relevant work has also been done by Kukimoto and Fujita [77] but this is concerned with FPGA s rather than general logic. In addition, this work restricted re synthesizable parts of the network to all nodes at a level, rather than a general re synthesis region. Other ....

D. Brand, "Incremental Synthesis," in Proc. Intl. Conf. on Computer-Aided Design, pp. 126--129, Nov. 1992.

....identical structures in their transitive fanins. Finally, the matchings implied by these nodes are combined into a high quality matching. We use both a greedy heuristic, as well as an exact formulation. Other approaches to incremental synthesis rely on knowing input correspondences. Brand et al. s [46] work on incremental synthesis, which identifies regions of commonality similar to our own, requires knowledge of input correspondences and can only detect regions that start at the inputs. We assume that any two primary inputs may match if they can take the same set of values. Burch et al. [47] ....

D. Brand, A. Drumm, S. Kundu, and P. Narain, "Incremental Synthesis," in Proc. Intl. Conf. on Computer-Aided Design, pp. 14--18, Nov. 1994.

....the network may have already been implemented in silicon at a lower level of the design hierarchy, and it can be inconvenient to change. Previous algorithms for the problem of incremental synthesis have dealt with post rectification (Watanabe et al. 2] and preserving cones of logic (Brand et al.[3]) in the design. Some relevant work has also been done by Kukimoto and Fujita [4] but this is concerned with FPGA s rather than general logic. In addition, this work restricted re synthesisizable parts of the network to all nodes at a level, rather than general re synthesis region. Other ....

D. Brand, "Incremental Synthesis," in Proc. Intl. Conf. on Computer-Aided Design, pp. 126-- 129, Nov. 1992.

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D. Brand, A. Drumm, S. Kundu, and P. Narain, "Incremental synthesis," in Proc. Int. Conf. Computer-Aided Design, 1994, pp. 14--18.

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