A. Chandra and K. Chakrabarty, "Combining Low-Power Scan Testing and Test Data Compression for System-On-a-Chip," Proc. IEEE/ACM Design Automation Conf. (DAC), pp. 166-169, June 2001. Home/Search Document Details and Download
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Controlling Peak Power during Scan Testing - Sankaralingam, Touba (2002) (1 citation) (Correct)
....dissipation per clock cycle over the entire test session. Previous work in low power scan testing has mostly focused on the problem of controlling heat dissipation by reducing the average power dissipation [Chou 94] Wang 94, 97ab, 99] Dabholkar 98] Girard 99a] Sankaralingam 00, 01] Chandra 01] Some designfor test (DFT) techniques reduce peak power in addition to average power. In [Hertwig 98] and [Gerstendrfer 99] logic is added to hold the output of the scan cells at a constant value during scan shifting thereby reducing power dissipation. This approach greatly reduces average ....
Chandra, A., and K. Chakrabarty, "Combining LowPower Scan Testing and Test Data Compression for System-on-aChip, " Proc. of Design Automation Conf., pp. 166-169, 2001.
A Simple and Reusable Test Access Mechanism for SOC.. - Theologitou.. (Correct)
....effective solutions. The literature is constantly enriched with interest ing results in the area of SoC testing [1] Some of the issues currently addressed by researchers relate to defi nitions of Test Access Mechanisms [2, 3, 4, 5] self testing methodologies [6, 7, 8] compaction schemes [9, 10] for reduction of test time, power and bandwidth con sumption of TAMs, BIST approaches [11] Another issue is the selection of test patterns and the methods for optimization of SoC validation and testing [12, 13, 14, 15] This work has been performed in the framework of the PRO 3 project, ....
Anshuman Chandra and Krishnendu Chakrabarty, "Combining low power Scan testing and test data compression for system-on-a-chip", Design Automation Conference (DA C)Las Vegas, USA, June 2001.
Test Data Compression and Test Resource - Partitioning For System-On-A-Chip (2003) Self-citation (Chandra Chakrabarty) (Correct)
No context found.
A. Chandra and K. Chakrabarty, "Combining Low-Power Scan Testing and Test Data Compression for System-On-a-Chip," Proc. IEEE/ACM Design Automation Conf. (DAC), pp. 166-169, June 2001.
Test Data Compression: The System Integrator's Perspective - Paul Theo Gonciari (2003) (Correct)
No context found.
A. Chandra and K. Chakrabarty. Combining Low-Power Scan Testing and Test Data Compression for System-on-a-chip. In DAC, volume 38, pp 113--120, June 2001.
Low-Cost Test For Core-Based System-On-A-Chip - Gonciari (2003) (Correct)
No context found.
A. Chandra and K. Chakrabarty, "Combining Low-Power Scan Testing and Test Data Compression for System-on-a-chip," in Proceedings ACM/IEEE Design Automation Conference (DAC), vol. 38, pp. 113--120, June 2001.
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