I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment",in DAC, pp. 151--155, 2001. Home/Search Document Details and Download
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Packet-based Input Test Data Compression Techniques - Erik Volkerink Ajay (2002) (4 citations) (Correct)
....and variable length encoding techniques. Compared to previous work, the techniques have several advantages. The proposed compression techniques are applied on multiple industrial designs and benchmark circuits, Mintest [28] Illinois Scan Architecture [20] FDR Codes [6] Linear Decompressors [30] Proposed Approach Circuit Name Number of Scan Flip Flops Number of Vectors Number of Bits Number of Vectors Number of Bits Number of Vectors Number of Bits Number of Vectors Number of Bits Number of Vectors Number of Bits S13207 700 233 163k 273 110k 236 31k ....
I. Bayraktaroglu, and A. Ogailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," IEEE Proc. of Design Automation Conference, pp. 151-155, 2001.
Packet-based Input Test Data Compression Techniques - Erik Volkerink Ajay (2002) (4 citations) (Correct)
....can be classified in the following categories: Loss less compression techniques [3, 5, 6, 9, 21] These techniques typically take advantage of certain sequences of bits in the vectors by encoding the sequences using a smaller sequence of bits. Compression techniques based on LFSR reseeding [7, 10, 17, 19, 23]: These techniques assume that a large proportion of the bits in the test vectors are unspecified (also called don t care bits) For every test vector, most of the techniques attempt to find one or multiple seeds for on chip Linear Feedback Shift Registers (LFSRs) or XOR networks such that the bit ....
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", Design Automation Conference, pp. 151-155, 2001.
Reducing Test Data Volume Using LFSR Reseeding with Seed.. - Krishna And Nur (2002) (5 citations) (Correct)
.... These techniques include using run length codes [Jas 98] statistical codes [Jas 99] Golomb codes [Chandra 00] frequency directed codes [Chandra 01] parallel serial scan chains (Illinois Scan Architecture) Hamzaoglu 99] virtual scan chains [Jas 00] combinational linear decompressions [Bayraktaroglu 01] Reddy 02] and mixing pseudo random ATPG bits [Khoche 02] These techniques involve storing the test vectors in a compressed form on the tester, and then transferring them to the chip where they are decompressed using on chip hardware. Another class of techniques involves reducing test vector ....
....It is interesting to note that in the degenerate case where the scan window size is equal to 1, then the seed is essentially decompressed through a linear combinational network and loaded immediately into one bit slice of the scan chains. This is effectively equivalent to what is proposed in [Bayraktaroglu 01] where they design a linear combinational network to expand a smaller input vector (which is essentially equivalent to a seed ) to fill one bitslice of a larger number of scan chains. The advantage of having a larger scan window size is that the ratio of the total number of scan cells in the ....
Bayraktaroglu, I., and A. Ogailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Proc. of Design Automation Conference, pp. 151-155, 2001.
A Unified Approach to Reduce SOC Test Data Volume, Scan.. - Chandra, Chakrabarty (2003) (Correct)
....form the basis for TRP [4] A particularly attractive feature of TRP based on compression methods is that it does not require any redesign of IP cores. Test data volume reduction techniques based on on chip pattern decompression are also presented in [9] 13] The compression scheme presented in [11] utilizes a linear mapping network to drive a large number of internal scan chains through a small number of external pins. The RESPIN method proposed in [9] uses the scan chains of one embedded core to decode test patterns for another core or interconnection. The technique based on geometric ....
I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," in Proc. ACM/IEEE Design Automation Conf., 2001, pp. 151--155.
An Efficient Test Vector Compression Scheme Using.. - Jas, Ghosh-Dastidar, .. (2003) (3 citations) (Correct)
.... serial full scan (PSFS) for reducing test time in cores is presented in [16] A technique to reduce test data and test time by using specially designed cores (cores with virtual scan chains) is presented in [26] An approach that uses a linear combinational expander circuit is described in [2]. The use of Golomb codes and frequency directed run length (FDR) codes for compressing test data have been demonstrated in [5] 7] respectively. The use of variable length input Huffman 0278 0070 03 17.00 2003 IEEE codes for SOC test data compression has been proposed in [14] A fixed to fixed ....
I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," in Proc. Design Automation Conf., 2001, pp. 151--155.
Test Application Time and Volume Compression Through.. - Rao, Bayraktaroglu.. (2003) Self-citation (Bayraktaroglu Orailoglu) (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment",in DAC, pp. 151--155, 2001.
Virtual Compression through Test Vector Stitching for Scan.. - Rao, Orailoglu (2003) Self-citation (Orailoglu) (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", in DAC, pp. 151--155, 2001.
A Novel Scan Architecture for Power-Efficient, Rapid Test - Ozgur Sinanoglu And (2002) Self-citation (Orailoglu) (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", in DAC, pp. 151--155, 2001.
Virtual Compression through Test Vector Stitching for Scan.. - Rao, Orailoglu (2003) Self-citation (Orailoglu) (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", in DAC, pp. 151--155, 2001.
Reducing Test Application Time Through Test Data Mutation.. - Reda, Orailoglu (2002) (6 citations) Self-citation (Orailoglu) (Correct)
....to alleviate timing constraints on the ATE. In order to be able to compress the test data, researchers have suggested various compression techniques coupled with building on chip decompression circuits to decompress the test data stream into test slices to be injected into the scan chains [9] [1], 7] 3] 8] The overriding goals in the design of compression techniques are comprised of a superior compression ratio and minimal hardware overhead. These often conflicting goals are both simultaneously achieved in the technique we herein propose through cost effective encodings of the flips ....
....problems. Experimental results are given in section 6, while Section 7 briefly summarizes the contributions of the paper. 2 Previous Work In response to the increasing testing time of digital circuits, researchers have suggested a variety of techniques to compress the test data [9] [1], 7] 3] 8] One of the suggested techniques utilizes Huffman encoding [7] to compress the most frequently occurring patterns. The patterns to be compressed are selected so as to minimize the area overhead by the on chip decompression network. The technique delivers acceptable compression ....
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I. Bayraktaroglu and A. Orailoglu. Test volume and application time reduction through scan chain concealment. In Proc. of Design Automation Conference, pages 151--155, 2001.
Nine-Coded Compression Technique with Application.. - Tehranipour, Nourani.. (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," in Proc. Design Automation Conf. (DAC'01), pp. 151-155, 2001.
Mixed RL-Huffman Encoding for Power Reduction and.. - Tehranipour.. (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," in Proc. Design Automation Conf. (DAC'01), pp. 151-155, 2001.
RL-Huffman Encoding for Test Compression and Power.. - Nourani, Tehranipour (1995) (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," in Proc. Design Automation Conf. (DAC'01), pp. 151-155, 2001.
Deterministic BIST Based on a Reconfigurable Interconnection - Lei Li And (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," Proc. ACM/IEEE Design Automation Conf., pp. 151--155, 2001.
On Combining Pinpoint Test Set Relaxation and Run-Length Codes - For Reducing Test (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," Design Automation Conference, pp.151-155, June 2001.
Test Data Compression: The System Integrator's Perspective - Paul Theo Gonciari (2003) (Correct)
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I. Bayraktaroglu and A. Orailoglu. Test Volume and Application Time Reduction Through Scan Chain Concealment. In DAC, volume 38, pp 151--155, June 2001.
Analysis of Test Application Time for Test Data Compression.. - Chandra, al. (2004) (Correct)
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I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction through Scan Chain Concealment," in Proceedings of ACM/IEEE Design Automation Conference, 2001, pp. 151--155.
Low-Cost Test For Core-Based System-On-A-Chip - Gonciari (2003) (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," in Proceedings ACM/IEEE Design Automation Conference (DAC), vol. 38, pp. 151--155, June 2001.
Nine-Coded Compression Technique with Application to.. - Tehranipour, Nourani.. (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," in Proc. Design Automation Conf. (DAC'01), pp. 151-155, 2001.
Deterministic BIST Based on a Reconfigurable Interconnection - Lei Li And (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test volume and application time reduction through scan chain concealment," Proc. ACM/IEEE Design Automation Conf., pp. 151--155, 2001.
Efficient Seed Utilization for Reseeding based Compression - Erik Volkerink Subhasish (2003) (2 citations) (Correct)
No context found.
I. Bayraktaroglu, and A. Ogailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment," IEEE Proc. of Design Automation Conference, pp. 151-155, 2001.
Efficient Seed Utilization for Reseeding based Compression - Erik Volkerink Subhasish (2003) (2 citations) (Correct)
No context found.
I. Bayraktaroglu and A. Orailoglu, "Test Volume and Application Time Reduction Through Scan Chain Concealment", Design Automation Conference, pp. 151-155, 2001.
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