Q. Jacobson and J. E. Smith. Trace preconstruction. In ISCA27, pages 37--46, 2000. Home/Search Document Details and Download
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Out-of-Order Instruction Fetch using Multiple Sequencers - Oberoi, Sohi (2002) (1 citation) (Correct)
....execution is able to overlap long latency operations with other useful instructions, out of order fetch can tolerate instruction supply delays like I cache misses by fetching other useful instructions while the miss is resolved. This mechanism can be thought of as just in time trace constructor [8] that can build multiple traces concurrently. We also observed that programs display a remarkably large amount of trace locality. In some benchmarks as many as 70 of the dynamic traces repeat within the next sixteen traces. It may be better to reuse the constructed traces rather than discarding ....
....cache misses, and proposed several ways of out of order renaming. Unlike the technique described in this paper, instruction fetch proceeded normally during most of the execution. Instructions were fetched out of order only on cache misses. Trace preconstruction was proposed by Jacobson et al. [8] to decrease the number of trace cache misses on programs with large working sets. Their focus was constructing a set of traces well ahead of the current trace so that when control reached that point in the future it would suffer no trace cache misses. Their technique maintains a stack containing ....
Q. Jacobson and J. E. Smith. Trace Preconstruction. In Proceedings of the 27th Annual International Symposium on Computer Architecture, pages 37--46, Vancouver, British Columbia, June 12--14, 2000.
Hardware Support for Prescient Instruction Prefetch - Aamodt, Chow, Hammarlund.. (2004) (1 citation) (Correct)
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Q. Jacobson and J. E. Smith. Trace preconstruction. In ISCA27, pages 37--46, 2000.
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