R. Raghavan and J. P. Hayes. On randomly interleaved memories. In SC90: Proceedings on Supercomputing '90, pages 49-58, November 1990.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....between the address of data and the bank is speci ed by a bank selection function that maps the address on a bank number. This function is similar in nature to a set index function. It could select some bits from the address, but it could do more complex calculations too [Rau91, FJL85, RH90, YL92, Smi82, Soh93] We use the term randomisation function for both set index functions and interleaving functions. Interleaving can be useful too for a level 1 data cache, especially when the superscalar paradigm is extended to higher issue widths [SF91, NVDB00] Current processors already ....

....to the same set, have their XOR based sum inside the nullspace. Previous studies of randomisation functions have used di erent models, e.g. functions operating on integers. In other work, the primary operation used by the randomisation functions is the XOR (exclusive or) Rau91, HIL89, FJL85, RH90, Soh93] Rau [Rau91] made the bridge from integer arithmetic to XOR arithmetic and showed how to construct XOR based functions that map strided vectors con ict free. Raghavan and Hayes [RH90] discovered some de ciencies in linear mapping functions (including Rau s) These functions cannot ....

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R. Raghavan and J. P. Hayes. On randomly interleaved memories. In SC90: Proceedings on Supercomputing '90, pages 49-58, November 1990.

....here gives a deeper and quantitative understanding of the performance implications of using this method. Moreover, in skewing schemes the address decoding hardware is designed such that the starting position in memory of successive rows are displaced relative one and other by a fixed distance [4,7,9]. Consequently, skewing corresponds to adding a number of dummy columns, with the difference that we do not have to waste any memory space for the dummy columns. This means that the bound presented here is valid also for skewed memory systems. Under ideal circumstances, systems where t = m = 2 ....

R. Raghavan and J. P. Hayes, "On Randomly Interleaved Memories", In Proceedings of Supercomputing '90, New York, 1990, pp. 49-57.

....given toward improving the speed of the DRAM itself. In this paper we discuss different methods for improving the latency of the DRAM accesses, and propose methods that could be used to achieve the best DRAM performance. One way to improve the memory access time is through bank interleaving [1] [5], 7] If the memory is divided into multiple banks, the banks can be accessed simultaneously. There are two problems with bank interleaving. The first is the requirement of a large memory because of the large size of the single DRAM chips [1] For example, if the system uses the 4 M bit chips ....

R. Raghavan and J.P. Hayes, On randomly interleaved memories, in Proc. Supercompu. '90 , pp. 49-58, Nov. 1990.

.... performance of the improved DRAM design (fast page or cache DRAM) depends on the ratio of accesses that could be found in the fast page or internal cache (hit rate) Memory designers have successfully used multi bank interleaving to increase the hit rate for systems using fast page or cache DRAM [2,3,5,7]. The introduction of new powerful processors with large built in caches, the references from processors to main memory is intercepted by this cache. Only misses from the processor internal cache goes to the main memory. Misses tend to have poor locality of references compared to un intercepted ....

R. Raghavan and J.P. Hayes, On randomly interleaved memories, in Proc. Supercompu. '90 , pp. 49-58, Nov. 1990.

....than the simple modulo powerof two. Lawrie and Vora proposed a scheme using prime modulus functions [16] Harper and Jump [11] and Sohi [24] proposed skewing functions. The use of XOR functions was proposed by Frailong et al. 5] and pseudo random functions were proposed by Raghavan Hayes [17] and Rau et al. 18] 19] These schemes each yield a more or less uniform distribution of requests to banks, with varying degrees of theoretical predictability and implementation cost. In principle each of these schemes could be used to construct a conflict resistant cache by using them as the ....

R. Raghavan and J.P. Hayes, "On Randomly Interleaved Memories", in Proc. Supercomputing `90, pp. 49-58. 22

....is obtained by allowing all the memory modules to operate in parallel. However, when the sequence of addresses does not access successive memory modules, as is the case in many scientific applications, then the gain in performance can be significantly less. The random interleaving techniques [107, 124, 74, 98] attempt to overcome this drawback by employing various methods to randomize the consecutive memory addresses issued by a processor. Most of these approaches involve logical operations on carefully selected address bits to effect the randomization. Address skewing is yet another technique [55] ....

Ram Raghavan and John P. Hayes. On randomly interleaved memories. In Proceedings of the Supercomputing '90 Conference, pages 1 -- 10, November 1990.

....Lawrie and Vora proposed a scheme using prime modulus functions [12] Harper and Jump [13] and Sohi [14] proposed skewing functions. The use of xor functions in parallel memory systems was proposed by Frailong et al. 15] and other pseudo random functions were proposed by Raghavan and Hayes [16], and Rau et al. 17] 18] These schemes each yield a more or less uniform distribution of requests to banks, with varying degrees of theoretical predictability and implementation cost. In principle each of these schemes could be used to construct a conflict resistant cache by using them as the ....

R. Raghavan and J. Hayes, "On randomly interleaved memories, " in Proc. Supercomputing '90, pp. 49--58, 1990.

....overhead. A variety of memory interleaving, skewing, and random mapping schemes have been developed to reduce contention in shared memory accesses. Some of these provide conflict free access for a limited set of access patterns [12, 13] while others im 11 prove the average access performance [14, 15, 16]. The Monarch, a massively parallel processing computer being developed by BBN, is an example which applies random mapping on memory addresses to reduce memory and network contention [11] The Monarch also employs read combining to reduce contention. In order to support the read combining, all ....

R. Raghavan and J. P. Hayes, "On randomly interleaved memories," in Proceedings of the Supercomputing '90 Conference, 1990.

....we study to what extent we can ignore the effects of multiple memory locations residing in a single bank when using pseudo random mappings of memory locations to memory banks. Many researchers have studied the effect of randomly mapping memory to banks (e.g. MV84, KU86, Ran91, Val90a, ACC 90, RH90, Rau91, IC93] If there is sufficient parallel slackness (extra parallelism) so that each bank is receiving multiple requests, it has been shown [MV84, KU86, Ran91, Val90a] that with high probability the memory references will be reasonably balanced across the banks. These results, however, ....

.... mapping memory locations into banks is a standard technique to reduce module map contention (contention due to multiple memory locations being mapped to the same bank) in simulations of shared memory on machines with a fixed set of memory modules (see, e.g. MV84, KU86, Ran91, Val90a, ACC 90, RH90, Rau91, IC93] The primary advantage is that it ensures that concurrently requested memory locations will likely be distributed evenly across the banks. In this section we study to what extent we can ignore the module map contention ( when randomly mapping memory to banks. In particular we ....

R. Raghavan and J. P. Hayes. On randomly interleaved memories. In Proceedings Supercomputing '90, pages 49--58, November 1990.

....in [17] n 4. Adapted Order Sequence This section introduces an order to reference memory modules that avoids conflicts when the rate request of all the concurrent vector streams, to every memory module is less than or equal to the memory service rate. R. Raghavan an J.P. Hayes with theorem 6 in [4], prove the conditions to be fulfilled by N vector streams to be conflict free. From the theorem we can deduce that a sufficient condition for not having conflicts is that all the vector streams must have the same stride, that is to say, all the vector streams reference the memory modules ....

....that can use bases other than two, is segmented to compute several values in parallel. The number of cycles needed is small because C s is small (a few bits) Also can be previously computed. The number of parameters that have to be calculated is comparable to the number needed for other proposals [1,4,6]. Also, most of the parameters can be determined by the compiler. To store previous values of the variable A, registers (RA in the algorithm of figure 6) are needed to compute later values of A. In [17] we justify the correctness of this implementation. As an example, for a memory system with M=16 ....

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R.Raghavan and J.P.Hayes, On Randomly Interleaved Memories, Proc. Supercomputing'90, november 1990, pp. 49-58.

....shown is for only 8 processors) Second, we study to what extent the effects of multiple memory locations residing in a single bank can be ignored, when using random mappings of memory locations to memory banks. Many researchers have studied the effect of randomly mapping memory to banks (e.g. [36, 32, 41, 52, 2, 40, 42, 35, 28]) If there is sufficient parallel slackness (extra parallelism) so that each bank is receiving multiple requests, it has been shown [36, 32, 41, 52] that with high probability the memory references will be reasonably balanced across the banks. These results, however, assume that there is no ....

.... random memory mappings Randomly mapping memory locations to memory banks is a standard technique to reduce module map contention (contention due to multiple memory locations being mapped to the same bank) in simulations of shared memory on machines with a fixed set of memory modules (see, e.g. [36, 32, 41, 52, 2, 40, 42, 35, 28, 24]) The primary advantage of random mapping is that it ensures that concurrently requested memory locations will likely be distributed evenly across the banks. In this section we study to what extent we can ignore the module map contention ( when randomly mapping memory to banks. In particular we ....

R. Raghavan and J. P. Hayes. On randomly interleaved memories. In Proceedings Supercomputing '90, pages 49--58, November 1990.

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Raghavan, R. and Hayes, J. P. (1990) On randomly interleaved memories. In Proc. Supercomputing '90,New York, November, pp. 49--58.

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