S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli. Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000 pp. 412-418.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....style for the control logic of a high performance processor. It is not only because a dynamic PLA can provide high speed but also because the wire delay is easy to predict in the logic design phase. It was reported in literature [7] that a 1G Hz microprocessor utilizes the dynamic PLA style. In [4], the authors also showed that the delay of using a network of dynamic PLAs is 15 faster than that the delay of using the standard cell approach for some benchmark circuits. Our experiments on 0.18g TSMC technology also showed that a X86 controller design using a dynamic PLA style could be twice ....

....transitions from low to high while product lines P2 and P4 stay at low. The crosstalk noise produces noise glitches on product lines P2 and P4, which may discharge output el. If the crosstalk noise is large enough, it may cause functional error in el. To prevent the cross talk problem, Khatri [4] uses a static weak pull up device to prevent the crosstalk noise in dynamic PLA. Xiao [11] prevents the cross talk noise by increasing transistor size or spacing for a given layout. Several eflbrts are proposed to reduce the crosstalk effect in the routing [2] 4] 5] 8] 11] In general, most ....

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S. P. Khatri, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric", Proc. ICCAD, pp. 412-418, 2000.

....1 Introduction and Previous Work Programmable Logic Arrays (PLAs) are being rediscovered as an efficient implementation style for highperformance circuits. For example, in the Gigahertz processor [9] performance critical parts of the control were implemented using single PLAs. Recent work [8] demonstrates that a circuit implementation based on a network of approximately equal sized PLAs yields a fast, compact, and cross talk resistant design. The use of minimum sized transistors in the CAD Research Group, Department of EECS, University of California, Berkeley, CA 94720. VLSI CAD ....

....proposed to improve the area or the routability of a multilevel circuit by wire removal and or substitution. In this paper, we focus on Sets of Pairs of Functions to be Distinguished (SPFDs) as a candidate technique for wire removal. The circuit is assumed to be implemented using a network of PLAs [8]. We show that SPFD based wire removal can remove wires that redundancy removal based techniques cannot. SPFDs [16] were introduced in the context of FPGA optimization. In [2] this technique was refined and adapted to multi level networks, while its application to logic optimization was described ....

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S. P. Khatri, R. K. Brayton, and A. Sangiovanni-Vincentelli. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. In Proceedings of the International Conference on Computer-Aided Design, Nov 2000. To appear.

....the scope of this paper. Condition (2) is present because control and data nodes require different sets of logic and data path for implementation. Condition (3) is due to instruction encoding and register file limitations. Condition (4) guarantees deterministic and correct functionality. In [18] Khatri introduced a clustering algorithm with a similar definition of clubs, for the mapping from a logic network to a network of PLAs. Although it does not satisfy our clubbing constraints, our clubbing algorithm, outlined in Figure 2, is based on this. The network is first optimized and ....

S. P. Khatri, R. K. Brayton, and A. Sangiovanni-Vincentelli. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 412--18, Nov. 2000.

....the scope of this paper. Condition (2) is present because control and data nodes require different sets of logic and data paths for implementation. Condition (3) is due to instruction encoding and register file limitations. Condition (4) guarantees deterministic and correct functionality. In [18] Khatri introduced a clustering algorithm, with a similar definition of clubs, for mapping from a logic network to a network of PLAs. Although it does not satisfy our clubbing constraints, our clubbing algorithm, outlined in Figure 2, is based on this. The network is first optimized and ....

S. P. Khatri, R. K. Brayton, and A. Sangiovanni-Vincentelli. Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. In Proc. of the Intl. Conf. on Computer-Aided Design, pages 412--18, Nov. 2000.

....(a Boolean network) A common approach is to optimize both the entire network as well as each node, and then transform the circuit to a network of library cells via technology mapping. A natural step is to build a network of PLAs (NPLA) from the minimized network without technology mapping [10]. Thus some desirable features of single PLAs such as technology mapping free synthesis are preserved. However, NPLAs require placement and routing and the placement of PLAs is not at the gate but at the block level. So far, block level placement is not as well developed as gate level placement. ....

....placement of PLAs is not at the gate but at the block level. So far, block level placement is not as well developed as gate level placement. Also, even though each PLA in the NPLA is regular, global regularity is low because of placement and routing (this can also require additional metal layers [10]) In fact, global regularity of the NPLAs may be even worse than for standard cells, which have a row structure at least. To eliminate global irregularity of NPLAs caused by placement and routing, a multiple PLA structure called River PLA (RPLA) is proposed. Given a Boolean network, the nodes ....

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S. Khatri, R. Brayton and A. Sangiovanni-Vincentelli, "Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric", Proceedings of ICCAD, Nov 2000, 412-418

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S. Khatri, R. Brayton, A. Sangiovanni-Vincentelli. Cross-talk Immune VLSI Design using a Network of PLAs Embedded in a Regular Layout Fabric. ICCAD 2000 pp. 412-418.

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