P. Patra and U. Narayanan, "Automated phase assignment for the synthesis of low power domino circuits," in Proc. ICCAD, pp. 379--384, 1999.  Home/Search Document Details and Download
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Dual-Monotonic Domino Gate Mapping and Optimal Output Phase.. - Min Zhao Sachin (Correct)
....It was shown that both methods can reduce the area of the mapped circuits significantly with very limited computation overhead. By replacing the area cost of logic trees with power cost, we expect our 0 1 ILP of output phase assignment can serve the power minimization objective proposed in [7] similarly. ....
P. Patra and U. Narayanan, "Automated phase assignment for the synthesis of low power domino circuits," in Proc. ICCAD, pp. 379--384, 1999.
Domino Logic Synthesis Minimizing Crosstalk - Kim, Narayanan, Kang (2000) (1 citation) Self-citation (Narayanan) (Correct)
....[12, 11] or ATPG method [7] After the inverter elimination, if an inverter is found on output boundary, the output is said to be in a negative phase. Otherwise, the output is said to be in a positive phase. The relationship between power consumption and output phases have been studied in [10]. 1 2 3 4 5 Column Track n1 [C4] n2 [C5] n3 [C2] n5 [C6] n9 [C5] n10 [C6] n11 [C6] 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 Column Track n4 [C1] n3 [C2] n2 [C5] n1 [C4] n7 [C2] n8 [C5] n5 [C6] n10 [C6] n11 [C6] n9 [C5] n6 [C3] b) 0 1 2 3 4 5 6 ....
P. Patra and U. Narayanan. Automated phase assignment for the synthesis of low power domino circuits. In Proc. ACM/IEEE Design Automation Conf., pages 379--384, 1999.
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