R. Schreiber et al. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 31(2):127--142, Jun. 2002. Home/Search Document Not in Database Summary Related Articles Check |
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A Scheduling Algorithm for Optimization and Early Planning in .. - Memik, Kastner (Correct)
....descriptions of applications, such as from a high level programming language (e.g. C, C ) This approach offers designers a very convenient and familiar computational model. There are several proposed compilation flows from a high level of abstraction to hardware [32] 14] 12] 20] 13] [28]. Figure 1 depicts an example flow for automatic mapping of applications onto various hardware platforms. The application described in a high level programming language is processed by the compiler stage. The compiler generates an intermediate representation (IR) and performs several ....
R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, R. B. Rau, D. Cronquist, and M. Sivaraman. Pico-npa: High-level synthesis of nonprogrammable hardware accelerators, 2001. HPL-2001-249 Technical Report.
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....may be easily simulated or even synthesized. This will permit the rapid exploration of the architectural space and will complement several well founded methodologies that have emerged to ameliorate the engineering costs associated with exploring the design space of custom computing components [11, 16, 17]. The contributions of our work are as follows: 1. We propose PD XML, a generic and extensible methodology for describing, simulating and implementing instruction set architectures. Information is organized into two entities: one about storage, and the other about the instruction set. 2. We ....
R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.
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R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 31(2), June 2002.
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R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist and M. Sivaraman. PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. Journal of VLSI Signal Processing, 31, 2002, pp. 127-142.
Bitwidth Cognizant Architecture Synthesis of.. - Mahlke.. (2001) (3 citations) Self-citation (Schreiber) (Correct)
....resources where each resource can be used to execute any compatible operation, resources are allocated in clusters. Within each operation cluster, we allocate (by solving a small mixed integer linear program) a set of FUs that is powerful enough to perform the cluster operations at the desired II [4]. Each cluster of FUs is then characterized by a machine description for use by the Elcor software pipeliner. Hardware is synthesized by first generating a software schedule that decides on which FU and at what time each operation occurs, and then, by more mechanically generating a datapath during ....
R. Schreiber et al., "PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators," Journal of VLSI Signal Processing, vol. to appear, 2001.
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R. Schreiber et al. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 31(2):127--142, Jun. 2002.
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R. Schreiber et al. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 31(2):127--142, 2002.
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R. Schreiber, S. Aditya (Gupta), B.R. Rau, S. Mahlke, V. Kathail, B. Ra. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.
Compiler-directed Synthesis of Multifunction Loop.. - Fan, Kudlur, Park, Mahlke (Correct)
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R. Schreiber et al. PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. Journal of VLSI Signal Processing, 31(2):127--142, 2002.
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R. Schreiber et al. PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. Journal of VLSI Signal Processing, 31(2):127--142, 2002.
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R. Schreiber et al. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 31(2):127--142, Jun. 2002.
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R. Schreiber, S. Aditya, S. Mahlke, V. Kathail, B. R. Rau, D. Cronquist, and M. Sivaraman, "PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators," Tech. Rep., HP Laboratories, Palo Alto, 2001.
Spatial Computation - Budiu, Venkataramani, Chelcea.. (2004) (Correct)
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R. Schreiber, S. Aditya (Gupta), B.R. Rau, S. Mahlke, V. Kathail, B. Ra. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.
ACRES Architecture and Compilation - Ang, Schlansker (2004) (Correct)
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R. Schreiber, et al. PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. Technical Report, HPL-2001-249, 2001.
PICO: Automatically Designing Custom Computers - Kathail, al. (2002) (20 citations) (Correct)
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R. Schreiber et al., "PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators," J. VLSI Signal Processing, vol. 31, 2002, pp. 127142.
Spatial Computation - Budiu (2003) (Correct)
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R. Schreiber, S. Aditya (Gupta), B.R. Rau, S. Mahlke, V. Kathail, B. Ra. Rau, D. Cronquist, and M. Sivaraman. PICO-NPA: High-level synthesis of nonprogrammable hardware accelerators. Journal of VLSI Signal Processing, 2001.
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