CONG,J.AND DING,Y. 1996. Combinational logic synthesis for LUT based field programmable gate arrays. ACMTrans. Des. Automat. Electron. Syst. 1,2,145--204.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....product term mode memory arrays and give an overview of Hybrid Map, an algorithm that targets product term memory arrays. 2.4.1 Terminology Before we discuss algorithms for mapping logic to memory, we will first describe the terminology used. Much of this terminology has been adapted from [8]. The input to the algorithm is a network of 4 LUTs. A network is a directed graph (collection of directed edges and vertices) that represents the input circuit. Each vertex in the graph is called a node, and represents a 4 LUT. An edge is a connection between two nodes, and thus represents a ....

Cong, J. and Ding, Y., "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," in ACM Transactions on Design Automation of Electronic Systems, vol. 1, no. 2, April 1996, pp. 145-204.

....of a circuit with respect to a given design style. Clearly, di erent representations will lead to di erent circuit placement and routing characteristics. For an overview of logic synthesis consider [Villa et. all (1997) a) Array (b) Custom design (c) Standard cell Fig. 2. Layout styles and [Cong and Ding (1996)] and for its application to evolutionary algorithms consider [Drechsler (1998) For individual genetic algorithm investigations examining logic synthesis issues consider [Becker and Drechsler (1994) Ohmori and Kasai (1997) Thomson and Miller (1997) and [Verumi and Verumi (1991) Once a ....

Cong J. and Ding Y., Combinational logic synthesis for LUT Based Field Programmable Gate Arrays, ACM Transactions on the Design of Electronic Systems, volume 1, number 2, 1996, 145-204

....logic synthesis are refined covering algorithms [Cou92, Lia97, Gol97] optimizations on networks described using black boxes [Liu97] power optimization [Nar97, Tiw96] etc. Similarly, the research activity in technology mapping has been streamlined towards library [Gav97, Ped96] and LUT targeted [Hua96, Con96a] algorithms. Our approach is the first to define a set of protocols for information hiding into a design at the combinational logic synthesis level. Such watermarking technique provides security against sophisticated reverse engineering attacks [And98] enables concurrently physical layout ....

....uses the structural properties of the input network. Such an algorithm facilitates algebraic decompositions of the input logic network to generate a new network of smaller gates (gate decomposition) and then covers it with cells or LUTs. A good survey of techniques of this class is presented in [Con96a, Mic94, Hac96]. 3.3. The Watermarking Desiderata Recently proposed, Strawman initiative [VSI97] of the Development Working group on Intellectual Property Protection calls for the following desiderata for techniques which act as deterrents in order to properly ensure the rights of the original designers: ....

[Article contains additional citation context not shown here]

J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. Trans. on Design Automation of Electronic Systems, Vol.1, no.2, pp.145-204, 1996.

....of CLBs can also be configured into ICLBs. In the Xilinx XC4000E series (Fig. 1(b) c) each CLB can be configured to (i) one 3 LUT and two 4 LUTs, ii) one 5 LUT, or a few other non ICLB configurations [9] The minimum area LUT mapping problem has been studied extensively. The survey paper of [2] gives a good overview of the techniques used and the results obtained. This problem was shown to be NP complete for k 3 [3, 10] and polynomial time solvable for k = 2 [8] A polynomial time algorithm (for any k) was given for tree networks in [3] However, minimizing the number of LUTs does not ....

....technology mapping of a general network, N . As the problem is hard, we use the very common and effective strategy of tree based mapping [6] that proceeds in three stages: N is first partitioned into disjoint trees: each PO node and each node with multiple fanout defines a tree in the partition [2]. Each tree is then mapped independently. In the final stage, the mapping solutions of all the trees are combined to give a good mapping solution for N . A similar approach was studied in [5] However, their method for mapping a tree is a heuristic, with no guarantees on the solution quality. As ....

[Article contains additional citation context not shown here]

Jason Cong and Yuzheng Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. ACM Trans. on Design Automation of Electronic Systems, 1(2):145--204, Apr. 1996. Tutorial and Survey Paper.

....Section 5 then evaluates the algorithms and answers the first question listed above. Finally, Section 6 compares single and dual port arrays, and answers the second question listed above. 2 Preliminaries 2. 1 Terminology In this paper, we will use the following terminology (primarily from [11]) The combinational part of a circuit is represented by a directed acyclic graph G#V;E# where the vertices V represent combinational nodes, and the edges E represent dependencies between the nodes. V also contains nodes representing each primary input and output of the circuit. Flip flop inputs ....

J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp. 145--204, April 1996.

....and p Delta a 2 k 2 LUTs. The ICLB mapping problem and the notion of covering are defined more precisely in section 2. The closely related problem of mapping a given combinational circuit using single LUTs has been studied extensively over the last decade. The survey paper by Cong and Ding [2] gives a good overview of the techniques used and the results obtained in this direction. The goal is to minimize area which is measured by the number of LUTs used in the mapping. This LUT mapping problem was shown to be NP complete for k 3 [3, 9] and polynomial time solvable for k = 2 [7] For ....

....very common and effective strategy of tree based mapping [6] Such a strategy proceeds in three stages. In the first stage the network is partitioned into disjoint trees uniquely in a standard fashion: each PO node and each node with outdegree greater than one defines a tree in the partition. See [2] for more details. In the second stage, each tree is mapped independently using an efficient algorithm for trees. In the third stage, the mapping solutions of all the trees are combined to get a good mapping solution for the entire network. Algorithm Network ICLB Map(N ; k 1 ; k 2 ) begin ....

[Article contains additional citation context not shown here]

Jason Cong and Yuzheng Ding. "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays". ACM Transactions on Design Automation of Electronic Systems, 1(2):145--204, April 1996. Tutorial and Survey Paper.

....approach as This work is partially supported by SRC 98 DC 324. library based technology mapping since one needs to generate pattern graphs for all 2 2 k k input functions. Based on this observation many ideas have been proposed for the FPGA mapping problem again under different cost criteria [4]. As for minimum area mapping Levin et al. 10] and Farrahi et al. 6] proved that the problem is NP hard for k = 4 and k 5 respectively. Minimum delay mapping, on the other hand, was shown for LUT based FPGAs to be solvable in polynomial time by Cong et al. in [1, 2] Here the given circuit is ....

J. Cong and Y. Ding. Combinational logic synthesis for LUT based field programmable gate arrays. ACM Transactions on Design Automation of Electronic Systems, 1(2):145--204, April 1996.

....technology. It is not practical to follow the same approach as library based technology mapping since one needs to generate pattern graphs for all 2 2 k k input functions. Based on this observation many ideas have been proposed for the FPGA mapping problem again under different cost criteria [4]. As for minimum area mapping Levin et al. 11] and Farrahi et al. 7] proved that the problem is NP hard for k = 4 and k 5 respectively. Minimum delay mapping, on the other hand, was shown for LUT based FPGAs to be solvable in polynomial time by Cong et al. in [1, 2] Here the given circuit is ....

J. Cong and Y. Ding. Combinational logic synthesis for lut based field programmable gate arrays. ACM Transanctions on Design Automation of Electronic Systems, 1(2):145--204, April 1996.

No context found.

CONG,J.AND DING,Y. 1996. Combinational logic synthesis for LUT based field programmable gate arrays. ACMTrans. Des. Automat. Electron. Syst. 1,2,145--204.

No context found.

J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Trans. Design Automat. Electron. Syst. vol. 1, no. 2, pp. 145--204, 1996.

No context found.

Cong, J. and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, 2, pp. 145-204, 1996.

....little or no apparent data parallelism. Our current effort focuses on accelerating a number of logic synthesis and optimization algorithms. There have been extensive studies into using various logic synthesis techniques to optimize FPGA designs. A summary of many of those studies can be found in [CoDi96], but this work is among the first attempt to use FPGAs to accelerate computation intensive logic synthesis algorithms. Our work studies the feasibility of designing and implementing reconfigurable coprocessors used as accelerators for a class of commonly used logic synthesis algorithms. This ....

Cong, J. and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, 1996 V1, 2 145-204.

....been published in recent years, for example, tree based Chortle family algorithms by Francis et al. 4] 5] the depth optimal FlowMap algorithm by Cong and Ding [1] the synthesis based MIS pga family by Murgai et at. 7] 8] and the a rea minimal mapping algorithm Praetor by Cong et al. [2] See [3] for a more comprehensive survey. However, none of these a lgorithms is designed specifically for incremental changes. Very few papers addressed the incremental design issues for FPGAs. Kukimoto et al. presented a redesign technique for FPGAs [6] However, 6] focused on completely keeping the ....

J. Cong and Y. Ding, Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays, ACM Trans. on Design Automation of Electronic Systems, Vol. 1, No. 2, April, 1996, pp. 145-204.

....Hac96] Recent improvements in combinational logic synthesis include refined covering algorithms [Lia97] optimizations on networks described using black boxes [Liu97] power optimization [Tiw96] etc. In addition, logic synthesis for FPGAs has been a very active research area (see survey in [Con96a]) 3. WATERMARKING DESIDERATA The recently proposed Strawman initiative [VSI97] of the Development Working group on IPP calls for the following desiderata for techniques which act as deterrents in order to properly ensure the rights of the original designers. Functionality Preservation. Design ....

....signature specific selection of a combination of network nodes. In the case of technology mapping of LUT based FPGAs, the described node selection phase is the last phase in the protocol. However, it is important to stress the implications of a specific phenomenon in this problem. Cong and Ding [Con96a] have identified a class of MFFC nodes which are more likely to appear in the final solution than the remaining nodes. We have statistically evaluated the impact of this phenomenon on the strength of the proof of authorship enabled by our approach. For each instance of the problem, we have ....

J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. Trans. on Design Automation of Electronic Systems, vol.1, no.2, pp.145-204, 1996.

....could be more cost effective than using PLBs to cover K input functions obtained from the decomposition of wide functions. However, the problem of matching wide functions to (LUT based) PLBs has not been understood well before. As a result, most existing technology mapping algorithms (see [4] for a comprehensive survey) focus on K LUT covering for area or delay minimization, or LUT to PLB packing for area minimization. Recently, Sasao and Butler [12] studied the bi decomposition f (X) h (g 1 (X 1 ) g 2 (X 2 ) of logic functions. They gave necessary and sufficient conditions for ....

Cong, J. and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, 2, pp. 145-204, 1996.

....collapsed networks into LUT networks directly. The objectives of these tasks include area or delay minimization, routability maximization, or a combination of them. A comprehensive survey of gate decomposition, LUT mapping, and logic synthesis algorithms for LUT based FPGAs can be found in [CoDi96]. The delay of an LUT network can be measured by the number of levels (or depth) in the network under the unit delay model. A number of algorithms were proposed in the past for delay oriented LUT mapping. We classify them into two classes. The first class of algorithms, such as Chortle d ....

Cong, J. and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, 2, pp. 145204, 1996.

....and Roth and Karp [17] in different forms. Recently, efficient decomposition algorithms [3, 14, 21] have been developed based on the functional representation of reduced ordered binary decision diagrams (ROBDD) 2] A comprehensive survey of the results on functional decomposition was given in [7]. In general, the encoding functions may depend on all variables in the bound set. A partially dependent decomposition produces encoding functions which are independent of some variables in the bound set. Methods to minimize the support of encoding functions during decomposition were recently ....

Cong, J. and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays," ACM Trans. on Design Automation of Electronic Systems, Vol. 1, 2, pp. 145-204, 1996.

....Hac96] Recent improvements in combinational logic synthesis include refined covering algorithms [Lia97] optimizations on networks described using black boxes [Liu97] power optimization [Tiw96] etc. In addition, logic synthesis for FPGAs has been a very active research area (see survey in [Con96a]) 3. WATERMARKING DESIDERATA The recently proposed Strawman initiative [VSI97] of the Development Working group on IPP calls for the following desiderata for techniques which act as deterrents in order to properly ensure the rights of the original designers. ffl Functionality Preservation. ....

....signature specific selection of a combination of K network nodes. In the case of technology mapping of LUT based FPGAs, the described node selection phase is the last phase in the protocol. However, it is important to stress the implications of a specific phenomenon in this problem. Cong and Ding [Con96a] have identified a class of MFFC nodes which are more likely to appear in the final solution than the remaining nodes. We have statistically evaluated the impact of this phenomenon on the strength of the proof of authorship enabled by our approach. For each instance of the problem, we have ....

J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. Trans. on Design Automation of Electronic Systems, vol.1, no.2, pp.145-204, 1996.

....logic synthesis are refined covering algorithms [Cou92, Lia97, Gol97] optimizations on networks described using black boxes [Liu97] power optimization [Nar97, Tiw96] etc. Similarly, the research activity in technology mapping has been streamlined towards library [Gav97, Ped96] and LUT targeted [Hua96, Con96a] algorithms. Our approach is the first to define a set of protocols for information hiding into a design at the combinational logic synthesis level. Such watermarking technique provides security against sophisticated reverse engineering attacks [And98] enables concurrently physical layout ....

....uses the structural properties of the input network. Such an algorithm facilitates algebraic decompositions of the input logic network to generate a new network of smaller gates (gate decomposition) and then covers it with cells or LUTs. A good survey of techniques of this class is presented in [Con96a, Mic94, Hac96]. 3.3. The Watermarking Desiderata Recently proposed, Strawman initiative [VSI97] of the Development Working group on Intellectual Property Protection calls for the following desiderata for techniques which act as deterrents in order to properly ensure the rights of the original designers: ffl ....

[Article contains additional citation context not shown here]

J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. Trans. on Design Automation of Electronic Systems, Vol.1, no.2, pp.145-204, 1996.

No context found.

J. Cong and Y. Ding. Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays. Trans. on Design Automation of Electronic Systems, Vol.1, no.2, pp.145-204, 1996.

No context found.

J. Cong and Y. Ding, "Combinational logic synthesis for LUT-based field-programmable gate arrays," ACM Transactions on Des. Automat. Electron. System, April, pp. 145 -- 204, 1996.

No context found.

J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," TODAES, ACM Trans. Design Automat. Electron. Syst., vol. 1, no. 2, pp. 145--204, Apr. 1996.

No context found.

J. Cong and Y. Ding, "Combinational logic synthesis for LUT based field programmable gate arrays," ACM Trans. Design Automation Electron. Syst., vol. 1, pp. 145--204, Apr. 1996.

No context found.

J. Cong and Y. Ding, "Combinational Logic Synthesis for LUT Based Field Programmable Gate Arrays", ACM Trans. on Design Automation of Electronic Systems, vol. 1, no. 2, pp. 145-204 April 1996.

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