L. C. Chen, S. K. Gupta and M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," Proc. Design Automation, Conf., June 2001. Home/Search Document Details and Download
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Timed Pattern Generation for Noise-on-Delay Calculation - Choi, Dartu, Roy (2002) (Correct)
....of a high end microprocessor design environment showed that the coupling could increase the delay by 30 on average, making performance predictions a fortune telling experience. This problem does not scale well for future process technologies as the timing margins are getting smaller [4]. The noise on timing scenario is described in Figure 1 for a gate with n aggressors. vict im driver rece iver vict im driver rece iver Figure 1 Noise on delay setup In static timing analysis (STA) 5] the circuit performance is estimated in a pattern independent manner where the delay ....
L. Chen, et al, "A New Gate Delay Model for Simultaneous Switching and Its Applications," DAC, pp.289-294, 2001.
On Modeling Cross-Talk Faults - Sujit Zachariah Yi-Shing (2003) (Correct)
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L. C. Chen, S. K. Gupta and M. A. Breuer, "A new gate delay model for simultaneous switching and its applications," Proc. Design Automation, Conf., June 2001.
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