Herbordt, M. C., and Weems, C. C. Experimental analysis of some SIMD array memory hierarchies. In Proc. of the 1995 Int. Conf. on Parallel Processing (1995), vol. 1: Architecture, pp. 210-214. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
A System for Evaluating Performance and Cost of SIMD.. - Herbordt, Cravy, Sam, .. (1999) Self-citation (Herbordt) (Correct)
....information about locality of references (the OPT results vary only slightly) On the worse side we use a hybrid policy: we use the information about temps and automatics to statically allocate the evaluation stack. The rest of the replacement is done randomly. Sample results are presented in [19]. We found the di erences to be surprisingly small, especially when it came to the critical result of curve knee location and certainly adequate in determining the range of designs suitable for further study. Optimize Code Besides register assignment, there are several aspects to reconstructing ....
Herbordt, M. C., and Weems, C. C. Experimental analysis of some SIMD array memory hierarchies. In Proc. of the 1995 Int. Conf. on Parallel Processing (1995), vol. 1: Architecture, pp. 210-214.
Preprototyping SIMD Coprocessors Using Virtual Machine.. - Martin Herbordt Self-citation (Herbordt Weems) (Correct)
....We also anticipate the trace driven datapath simulator to be relatively simple as MPA PEs have to worry about neither instruction fetch, nor control hazards. Cache evaluation Again, although no MPAs are currently being built with cached PEs we also see this as a future direction (see e.g. [11]) The cache evaluator takes as input the load store trace generated as described in the previous section. The memory model is assumed to be as in Figure 2. Standard cache analysis techniques are used to measure the performance in relation to cache size, block size, associativity, and policy. 8 ....
Herbordt, M. C., and Weems, C. C. Experimental analysis of some SIMD array memory hierarchies. In Proc. of the 1995 Int. Conf. on Parallel Processing (1995), vol. 1: Architecture, pp. 210--214.
Processor/Memory/Array Size Tradeoffs in the Design of SIMD.. - Martin Herbordt Self-citation (Herbordt Weems) (Correct)
....with a simple serial model. See Figure 2. Existing MPAs and MPA designs contain on chip memory in the range of 32 to 1024 bits. 2 Off chip memory typically consists of DRAM, although SRAM has also been used. Although no MPA has yet been built with PE cache, studies have shown the clear benefits [8]. The particular features we examine here are the register file size from 128 to 1600 bits and the cache size. We do not examine very small register file sizes because our programmer s model requires at least three 32 bit registers. We assume enough main memory to store all the data the programs ....
....that a system will be built with PE cache if that cache has not been designed to have a hit rate of over 90 . We therefore use two parallel rankings: register file size with no cache, and register file size with cache. Cache parameters required for this performance have been presented elsewhere [8]. 5 Experimental Results We have examined seven issues. Two involve the datapath, two memory, one memory with respect to datapath, and two overall cost performance. 1. As more resources are applied to the datapath, what features should be given priority Performance was measured for each ....
Herbordt, M. C., and Weems, C. C. Experimental analysis of some SIMD array memory hierarchies. In Proc. of the 1995 Int. Conf. on Parallel Processing (1995), vol. 1: Architecture, pp. 210--214.
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