Lucent Technologies, FPGA Data Book, 1998. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Fpga Routing Structures: A Novel Switch Block And Depopulated.. - Masud (1999) (3 citations) (Correct)
....various vendors. This will provide the reader sufficient background to follow the concepts presented and investigated in this thesis. 2. 1 FPGA ARCHITECTURE OVERVIEW There are many different FPGA architectures available from various vendors including Altera [19] Xilinx [20] Actel [21] Lucent [22], QuickLogic [23] and Cypress [24] Although the exact structure of these FPGAs varies from vendor to vendor, all FPGAs consist of three fundamental components: Logic Blocks, I O blocks, and the Programmable Routing. What comprises of a logic block, and how the programmable routing is organized ....
Lucent Technologies, FPGA Data Book, 1999.
Effect of the Prefabricated Routing Track Distribution on FPGA.. - Betz, Rose (1998) (2 citations) (Correct)
....number in the vertical channels Fig. 1(a) depicts an FPGA with such a directional bias. In essence, we are investigating if there is an intrinsic property of circuits that makes a directional bias more area efficient. If so, what amount of bias is best Commercial FPGAs with both unbiased routing [2, 3] and biased routing [4, 5] exist, so this question has commercial relevance. Second, should all routing channels in the same direction in an FPGA contain the same number of tracks or is a non uniform routing architecture, in which some channels are wider than others, preferable An example FPGA ....
....greatest challenge to routing completion and is normally the case manufacturers wish to optimize. In this study the number of I O pads that can fit into the height or width of a logic block is set to two. This number is commensurate with the relative sizes of I O pads and 4 LUTs in current FPGAs [2, 3, 5] and ensures that none of the 26 benchmarks is pad limited. Finally, we do not route the clock net (all the MCNC benchmarks use only a single clock) in sequential circuits, since this net is normally distributed through a special clocking network in commercial FPGAs. 3 Tuned Placement and Routing ....
[Article contains additional citation context not shown here]
Lucent Technologies, FPGA Data Book, 1998.
FPGA Routing Architecture: Segmentation and Buffering to.. - Betz, Rose (1999) (8 citations) (Correct)
....must devise routing architectures which are both fast and area efficient to create an FPGA that fully exploits the performance and density potential of deep submicron technologies. In this paper we investigate island style FPGA routing architectures; the FPGAs of Xilinx [3] Lucent Technologies [4], and Vantis [5] employ this style of routing architecture. A simplified view of an island style FPGA is shown in Figure 1. The routing architecture of an FPGA defines such features as: 1. The length of each routing wire segment (how many logic blocks a routing wire spans before terminating) 2. ....
....input and output pins are evenly distributed around the perimeter of the logic block, since [20] showed that this pin positioning is best. The number of I O pads that fit into the height or width of a logic block is set to four, in line with the relative sizes of pads and 4 LUTs of current FPGAs [3, 4, 5, 21]. With this assumption three of the twenty benchmark circuits we use (bigkey, des and dsip) are pad limited. We always map each circuit to the smallest square logic block array that has enough logic blocks and pads to accommodate it. Since commercial FPGAs normally distribute the circuit clock ....
[Article contains additional citation context not shown here]
Lucent Technologies, FPGA Data Book, 1998.
Configuration Prefetching Techniques for Partial - Reconfigurable Coprocessors.. Self-citation (Inc) (Correct)
....system, a greater portion of the program can be accelerated in the run time reconfigurable systems. This can lead to an overall improvement in performance. There are a few traditional configuration memory styles that can be used with reconfigurable systems, including the Single Context model [Xilinx94, Altera98, Lucent98], the Partial Run time Reconfigurable model (PRTR) Ebeling96, Schmit97, Hauck97] and the Multi Context model [DeHon94, Trimberger97] For Single Context FPGA shown in Figure 1, the whole array can be viewed as a shift register, and the whole chip area must be reconfigured during each ....
Lucent Technology Inc.. FPGA Data Book, 1998.
Design of High-Performance Field Programmable Gate Arrays for Data.. - Lee (2001) (Correct)
No context found.
Lucent Technologies, FPGA Data Book, 1998.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC