C. Hansen. MicroUnity's mediaprocessor architecture. IEEE Micro, pages 34--41, August 1996.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....Alpha processor of DEC Compaq [9] and Sun s MAJC 5200 processor, which feature two 4 threaded processors on a single die [10] Both processors are designed as high performance processors and will not be suitable for low cost embedded systems. However, the multithreaded MediaProcessor of MicroUnity [11] is specialized for multimedia appliances and the recent multithreaded Network Communication Processor of XStream Logic [15] is a dedicated network processor. Our Komodo project [4] explores the suitability of multithreading techniques in embedded real time systems. We propose multithreading as ....

C. Hansen. MicroUnity's mediaprocessor architecture. IEEE Micro, pages 34--41, August 1996.

....extremely well. Of course, an obvious drawback of this approach is that it provides no guarantee that other applications will run as well as the targeted application. While the current microprocessors for media applications (mediaprocessors) are claimed to target general applications in a domain [13], a custom fit processor targets a single application (although they remain programmable) We report on a method of system level synthesis of single or multiple application programmable processors. We use a benchmark suite consisting of complete applications written in a high level language [16] ....

C. Hansen, "MicroUnity's mediaprocessor architecture," IEEE Micro., vol. 17, pp. 34--41, 1997.

....3. Complex valued arithmetic support Operations on complex valued arithmetic is common in most wireless communication algorithms. This needs to be well supported by the communications processor. There have been DSP and GPP instructions for aligning and shuffling the real and imaginary parts [10] in computations such as the 4 FFT. However, typically the support for complex arithmetic is done in software and the real and imaginary parts are computed in parallel in hardware. 4. High I O bandwidth The high data rate requirements in 3G communication systems implies that a high I O ....

C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, pp. 34--41, August 1996.

....in TI s C60 case. Another way to solve this communication problem is to use a matrix memory as suggested by [2] or [3] However, memory is a critical system issue and often standard memory components are preferable. Thus, MicroUnity employed a wide standard memory, which contains grouped data [4]. Here, several data elements share one common address and are accessed in groups only. The processing is based on the Single Instruction Multiple Data (SIMD) principle. However, in MicroUnity s MediaProcessor a special communication unit is employed which accesses the group register file. In case ....

C. Hansen, "MicroUnity's mediaprocessor architecture," IEEE Micro, vol. 16, pp. 34--40, Aug 96.

....84 , and range as high as 253 . 1 Introduction The recent shift towards computation intensive multimedia workloads has resulted in a flourish of new multimedia extensions to current microprocessors [12, 15, 20, 23, 25, 30] Many new designs are targeted specifically toward the multimedia domain [5, 13, 16]. This trend is likely to continue as it has been projected that multimedia processing will soon become the main focus of microprocessor design [14] While different processors vary in the type and number of multimedia instructions offered, at the core of each is a set of short SIMD or superword ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, 16(4):34--41, Aug 1996.

.... Architectural enhancements found in commercial products include predicated instruction execution, VLIW execution and split register files [7, 31] Multi gauge arithmetic (or variablewidth SIMD) is found in the family of MPACT architectures from Chromatic [17] and the designs from MicroUnity [12]. Most of the multimedia extensions of programmable processors also adopt this architectural enhancement [22, 26] We investigate an approach to rapidly explore the design space of low power application specific programmable processors (ASPP) in particular mediaprocessors. We focus on a ....

C. Hansen. MicroUnity's MediaProcessor architecture. IEEE Micro, 17:34--41, 1997.

....SLP compilation. 43 7 Chapter 1 Introduction The recent shift toward computation intensive multimedia workloads has resulted in a variety of new multimedia extensions to current microprocessors [8, 12, 18, 20, 22] Many new designs are targeted specifically at the multimedia domain [3, 9, 13]. This trend is likely to continue as it has been projected that multimedia processing will soon become the main focus of microprocessor design [10] While different processors vary in the type and number of multimedia instructions offered, at the core of each is a set of short SIMD (Single ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, 16(4):34--41, Aug 1996.

....Hence, a stride insensitive memory system with a large bandwidth is needed. ffl Complex Valued Arithmetic Operations on complex valued arithmetic is also common in many wireless and DSP algorithms. There have been DSP and GPP instructions for aligning and shuffling the real and imaginary parts [31] in computations such as the FFT. However, typically the support for complex arithmetic is done in software and the real and imaginary parts are computed in parallel in hardware. ffl Approximate Computations There exists a class of arithmetic techniques that deal with the implementation of ....

Craig Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, pp. 34--41, August 1996.

....are applications with simple inner loop bodies. In his report, he extensively shows how inline templates can be used and how VIS can be enhanced. A new generation of true multimedia processors [14] such as the Philips TriMedia [6] the Mpact Media Engine [33] the MicroUnity MediaProcessor [16] and NVidia NV 1 [34] offer, in addition to subword parallelism, some new or reborn types of parallelism: 19 ffl very long instruction word (VLIW) ffl hardware micro threading, in which instructions from different threads are interleaved, ffl special functional units that perform typical ....

Greg Hansen. MicroUnity's MediaProcessor architecture. IEEE Micro, 16(4):34--41, August 1996.

....a stride insensitive memory system [1] with a large bandwidth is needed. Complex Valued Arithmetic Operations on complex valued arithmetic is also common in many wireless and DSP algorithms. There have been DSP and GPP instructions for aligning and shuffling the real and imaginary parts [2] in computations such as the FFT. However, typically the support for complex arithmetic is done in software and the real and imaginary parts are computed in parallel in hardware. 2 Approximate Computations There exists a class of arithmetic techniques that deal with the implementation of ....

C. Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, pages 34--41, August 1996.

....accesses. For example, the DSP56000 [1] and GEPARD [2] contain dual datamemory banks in order to overcome limited memory bandwidths. In these cases one goal of code generation is to maximize the number of parallel loads in order to reduce the execution time [3, 4] MicroUnity s media processor [5] and the M3 DSP platform [6] use a wide memory (group memory) Here, addressing of one memory word means to access all data words belonging to the addressed group. Processing is performed according to the single instruction multiple data (SIMD) principle, and does not allow to access arbitrary ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, 16(4):34--41, Aug 1996.

....Hardware Architectures 1997, IS T SPIE Symposium on Electronic Imaging: Science and Technology, February 10 14, 1997, San Jose, California, pp.122 133. generation of multimedia instructions for PA RISC processors, it is still a much smaller set than that now proposed for other processors [5 10]. It uses the existing microprocessor registers and functional units, like the Arithmetic Logical Unit (ALU) and the Shift Merge Unit (SMU) MAX2 features are added only if they have potential general purpose usage, in addition to providing significant speedup for media processing. Table 1 shows ....

Hansen C., "MicroUnity's MediaProcessor Architecture", IEEE Micro, vol. 16 no. 4, August 1996, pp. 34-41.

....systems. The shift towards VLIW architectures for media processors is readily apparent among the media processors developed after the TI MVP. Included in this group are Philips TriMedia s TM 1000 [35] 36] Chromatic Research s Mpact 1 [37] and Mpact 2 [38] MicroUnity s Broadband MediaProcessor [39], Samsung s MSP 1 [40] the joint Equator Hitachi MAP1000 [41] and Texas Instruments own addition, the VelociTI architecture [42] which includes the TMS320C62x fixed point processor and the TMS320C67x floating point processor. The primary exception to this trend of using VLIW processors is ....

C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, August 1996, pp. 34-41.

....by 46 . Speedups ranged from 1.24 to 6.70. 1 Introduction The recent shift toward computation intensive multimedia workloads has resulted in a variety of new multimedia extensions to current microprocessors [6, 10, 16, 18, 20] Many new designs are targeted specifically at the multimedia domain [3, 7, 11]. This trend is likely to continue as it has been projected that multimedia processing will soon become the main focus of microprocessor design [8] While different processors vary in the type and number of multimedia instructions offered, at the core of each is a set of short SIMD or superword ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, 16(4):34--41, Aug 1996.

....through caches. For either system, the criterion confirms that the fasted write policy was implemented. 2. 5 IEEE Compliant Floating Point Units Design of FPUs Recently industry has acknowledged that low precision floating point operations are very useful for real time 3D graphic applications [41, 22, 4, 18]. This observation reverses the previous trend of focusing on higher and higher precisions and sets a new performance goal. Namely, designing cheap IEEE floating point units (FPUs) capable of both double precision and single precision operations with a higher throughput for single precision ....

C. Hansen. MicroUnity's media processor architecture. IEEE Micro, 16(4), 1996.

.... Architectural enhancements found in commercial products include predicated instruction execution, VLIW execution and split register files [7, 31] Multi gauge arithmetic (or variablewidth SIMD) is found in the family of MPACT architectures from Chromatic [17] and the designs from MicroUnity [12]. Most of the multimedia extensions of programmable processors also adopt this architectural enhancement [22, 26] We investigate an approach to rapidly explore the design space of low power application specific programmable processors (ASPP) in particular mediaprocessors. We focus on a ....

C. Hansen. MicroUnity's MediaProcessor architecture. IEEE Micro, 17:34--41, 1997.

....2. Figure 10.5 shows the operation of this instruction. Various other forms of vector register permute can be envisaged. Somemedia processor architectures have included an extensive selection of permutation primitives that operate on the multiple subword elements held in a single wide data word [Han96] Existing media processing instruction sets have extremely short vectors that are processed in a one cycle, which makes fast permutations simpler to implement, and have no support for strided or indexed memory accesses, which makes element permutations more desirable. In contrast, vector ....

C. Hansen. Microunity's media processor architecture. IEEE Micro, 16(4):34--41, August 1996.

....Or, alternatively, short vectors are held in memory of a general purpose processor, and are operated on by multimedia extension instructions. These short vectors lack some of the flexibility of traditional vector architectures, but this is likely to change as multimedia instruction sets evolve [12, 29, 21]. Also, research focusing on new processormemory organizations, such as IRAM [20] would also benefit from vector technology. Vectors have inherent advantages when it comes to memory usage. A single instruction can exactly specify a long sequence of memory addresses. These may be consecutive, may ....

C. Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, pages 34--41, Aug. 1996.

....marginally better than the reference machine (1.02 to 1.05 speedups) but halves the register file cost. We believe that the results presented in this paper are not only relevant to the vector processor community but could also be of use in the near term for designers of multimedia instruction sets [19, 20, 21] [22, 23] A multimedia instruction set operates on short vectors (typically, no more than 8 elements) by exploiting sub word parallelism. Our results show that increasing the multimedia ISA s to accommodate vectors of 16 or 32 elements might provide significant speedups. ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, pages 34--41, August 1996.

....two clock cycles. Hardware cost is reduced by using only a half sized multiplication array and by sharing the rounding circuitry for both precisions. 1. Introduction Fast low precision floating point operations have been acknowledged recently as very useful for realtime 3D graphic applications [2, 5, 8, 12]. The new 3D graphic applications reverse the previous trend of focusing on higher and higher precisions and set a new performance goal. The new design goal is to design cheap IEEE floating point units (FPUs) capable of both double precision and single precision operations with a higher throughput ....

C. Hansen. MicroUnity's media processor architecture. IEEE Micro, Aug. 1996.

.... short vectors are held in memory of a general purpose processor, and are operated on by multimedia extension instructions [Lee96, PW96] These short vectors lack some of the flexibility of traditional vector architectures, but this is likely to change as multimedia instruction sets evolve [Han96, TONH96] Also, research focusing on new processor memory organizations, such as IRAM [PAY96] would also benefit from vector technology. All in all, we believe that, far from being dead, vector architecture will reappear in the short term in several fields. They will surely evolve from the ECL ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, pages 34--41, August 1996.

....such as queue lengths which are relevant to applications such as self routing datagrams. There are architectural inspirations for such active interconnects in processor pipelines, in ATM switches with intelligent port controllers (such as Fairisle and Sunshine [Mar96] and in media processor [Han96] architectures. 3.1 Applications Here are some applications of a small instruction budget architecture operating at high speed: ffl Mini firewalls: if( R IN (INVALID DST BITS INVALID SRC BITS) while ( END OF PACKET) R BUCKET R IN; else while ( END OF PACKET) R OUT R IN; If the ....

Craig Hansen. MicroUnity's MediaProcessor Architecture. IEEE Micro, pages 34--41, August 1996.

....a number of products based on new architectures that present hardware structures that are well matched to ILP compilers. Architectural enhancements found in commercial products include predicated instruction execution, VLIW, split register files and multi gauge arithmetic (or variable width SIMD) [5, 12, 17, 32]. Most of the multimedia extensions of generalpurpose processors also adopt similar architectural enhancements [20, 28] The arrival of production quality ILP compilers and commercial DSPs with VLIW architecture stimulated the idea of so called custom fit processors [9] Researchers have argued ....

C. Hansen. MicroUnity's MediaProcessor architecture. IEEE Micro, 17:34--41, 1997.

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C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, pp. 34--41, August 1996.

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C. Hansen, "MicroUnity's MediaProcessor Architecture," IEEE Micro, Aug. 1996, pp. 34-41.

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