J. Emer. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques, 2001.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....As discussed earlier, the cores we simulate are roughly modelled after cores of R4700, EV4 (Alpha 21064) EV5 (Alpha 21164) EV6 (Alpha 21264) and EV8 . EV8 is a hypothetical single threaded version of EV8 (Alpha 21464) The data on the resources for EV8 was based on predictions made by Joel Emer [2] and Artur Klauser [5] conversations with people from the Alpha design team, and other reported data. The data on the resources of the other cores are based on published literature on these processors. TABLE I CONFIGURATION OF THE CORES Processor R4700 EV4 EV5 EV6 EV8Issue width 1 2 4 6 ....

J. Emer. EV8:the post-ultimate alpha. In PACT Keynote Address (http://research.ac.upc.es/pact01/keynotes/emer.pdf, 2001.

....virtual machine environment where dynamic optimizations can be performed without modifying source binaries. Chip multiprocessor Jrpm is based on the Hydra chip multiprocessor (CMP) 32] Decreasing feature size and increasing transistor counts now allow chip multiprocessors to be a reality [6][14][24] 42] Chip multiprocessors combine several CPUs onto one die with a tightly coupled memory interface. In this configuration, inter processor sharing and communication costs are significantly less than in traditional multiprocessors. The reduced communication costs make it possible to take ....

Emer, J. Ev8: The post-ultimate alpha (keynote address). In PACT'01, Barcelona, Spain, September 2001.

....1101 1111 match combinations example of a datapath artifact where mismatches significantly outweigh the full matches. An additional challenge in the design of the issue queues for superscalar CPUs has to do with the delay of the tag matching and steering logic, which sits on the critical path [3, 4, 6]. We introduced the designs of two comparators that dissipate energy primarily on a full match, including a design (the PLSSC) that has a lower overall response time than the traditional design. Assuming a pipeline cycle time of 500 ps, the traditional comparators of Figure 1 leave about 380 ps ....

Emer, J. EV8: The post--ultimate Alpha. Keynote at International Conference on PACT, Sep. 2001.

....five cores have private L1 data and instruction caches and share a common L2 cache, phase lock loop circuitry, and pins. We chose the cores of these off the shelf processors due to the availability of real power and area data for these processors, except for the EV8 where we use projected numbers [10, 16, 6, 5]. All these processors have 64 bit architectures. Figure 1 shows the relative sizes of the cores used in the study, assuming they are all implemented in a 0.10 micron technology (the methodology to obtain this figure is described in the next section) It can be seen that the resulting core is only ....

....As discussed earlier, the cores we simulate are roughly modelled after cores of R4700, EV4 (Alpha 21064) EV5 (Alpha 21164) EV6 (Alpha 21264) and EV8 . EV8 is a hypothetical single threaded version of EV8 (Alpha 21464) The data on the resources for EV8 was based on predictions made by Joel Emer [10] and Artur Klauser [16] conversations with people from the Alpha design team, and other reported data [6, 5] The data on the resources of the other cores are based on published literature on these processors [1, 2, 3, 4] The multi core processor is assumed to be implemented in a 0.10 micron ....

J. Emer. EV8:the post-ultimate alpha. In PACT Keynote Address (http://research.ac.upc.es/pact01/keynotes/emer.pdf, 2001.

....flexible: parallel fetch units easily lend themselves to fetching multiple threads, fetching down both paths of frequently mispredicted branches, fetching instructions from reconvergent points, etc. The Alpha EV8 processor design included a fetch unit capable of a limited degree of parallelism [8]. It could fetch two discontiguous cache blocks simultaneously, like 3 a collapsing buffer. The blocks could be from two different threads, but each thread was fetched in order. 3 Parallel Fetch using Multiple Sequencers A sequential fetch unit contains a single sequencer which fetches one or ....

J. Emer. EV8: The Post--Ultimate Alpha. Keynote Address, 10th International Conference on Parallel Architectures and Compilation Techniques, 2001.

....and scheduled onto specially modified multiple issue processors. Moreover, multiple threads of execution can be generated from different programs and simultaneously executed on a wide issue processor. This technique, called simultaneous multithreading (SMT) 12] is being employed in Alpha EV8 [14], and Intel recently announced that the Xeon processor will support SMT. While earlier multithreaded schemes were implemented to hide cache misses, Zilles et al. 2] proposed multithreading to hide latency due to hardware exceptions in superscalar processors (i.e. TLB misses) Thus, exploiting ....

J. Emer, EV8: The Post-Ultimate Alpha, Conference on Parallel Architectures and Compiler Technology (PACT'01), Barcelona, Spain, Sept. 2001.

....thread state, SMT has percontext mechanisms for pipeline flushing, instruction retirement, subroutine return prediction, and trapping. Intel estimates that the modifications to an out of order superscalar necessary to support a four context SMT translated into only a 6 increase in chip area [27]. 2.1.1.2 SMT simulator core The SMT application level simulator is a detailed, stand alone, execution based simulator used extensively in previous SMT studies [22, 43, 44, 45, 46, 47, 59, 77, 81, 82, 83] It models the processor pipeline and memory system in great detail. While the simulator ....

EMER, J. Ev8: The post-ultimate alpha. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (September 2001).

....techniques, we improve performance under TLS by 6.2 28.5 for 6 of 14 applications, and by at least 2.7 for half of the other applications. 1. INTRODUCTION Multithreading within a chip is becoming increasingly commonplace: examples include the IBM Power4 [17] Sun MAJC [33] Alpha 21464 [9], HP PA 8800, and Sibyte BCM 1250 [4] While using this multithreaded hardware to improve the throughput of a workload is straightforward, using it to improve the performance of a single application requires parallelization. The ideal solution would be to convert sequential programs into parallel ....

EMER, J. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques (2001).

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J. Emer. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques, 2001. 155

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J. Emer. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques, 2001.

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Joel Emer. Ev8: the post-ultimate alpha. Keynote at International Conference on Parallel Architecture and Compilation Techniques, September 2001.

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J. Emer. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques, 2001. 155

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J. Emer. Ev8: The post-ultimate alpha.(keynote address). In International Conference on Parallel Architectures and Compilation Techniques, 2001.

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Joel S. Emer. EV8: the post-ultimate alpha. In International Conference on Parallel Architectures and Compilation Techniques, September 2001. Keynote address.

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J. Emer. EV8: The post-ultimate alpha. Keynote at PACT 2001.

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J. Emer. EV8:The Post-ultimate Alpha. In PACT Keynote Address, Sept. 2001.

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J. Emer. EV8:The Post-ultimate Alpha. In PACT Keynote Address, Sept. 2001.

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Emer, J. EV8: The post--ultimate Alpha. Keynote at International Conference on PACT, Sep. 2001.

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