Ho-Seop Kim and James E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In Proceedings of the 29th Annual International symposium on Computer architecture, pages 71--81. IEEE Computer Society, 2002.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....typically a performance loss associated with the use of a clustered register file in VLIW processors [12] With CODE, the clustered VRF is transparent to software and decoupling eliminates the performance overhead. The Alpha 21264 [14] the Multicluster processor [11] and the ILDP architecture [17] use clustering techniques to simplify the register file of an OOO wide issue engine. The first two assign architectural registers to clusters in a static manner. ILDP and CODE use renaming to allow flexible assignment of registers to clusters. All clustered superscalar approaches require issue ....

H. Kim et al. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In the Proceedings of the 29th Intl. Symp. on Computer Architecture, pages 71-- 81, Anchorage, AL, May 2002.

....problem by organizing their resources into replicated units on the chip. Communication within a unit takes one cycle, but communication between units incurs one more or additional cycles of delays. Examples of spatial architectures include clustered VLIWs, Raw [23] Grid processors [20] and ILDPs [11]. Instruction scheduling is an important optimization problem on spatial architectures. On these architectures, the instruction scheduler has to partition instructions across the computing resources. While instruction schedulers on traditional architectures only need to assign instructions to ....

Ho-Seop Kim and James E. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, AL, May 2002.

....problem by organizing their resources into replicated units on the chip. Communication within a unit takes one cycle, but communication between units incurs one more or additional cycles of delays. Examples of spatial architectures include clustered VLIWs, Raw [23] Grid processors [20] and ILDPs [11]. Instruction scheduling is an important optimization problem on spatial architectures. On these architectures, the instruction scheduler has to partition instructions across the computing resources. While instruction schedulers on traditional architectures only need to assign instructions to ....

Ho-Seop Kim and James E. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, AL, May 2002.

....without leading to a large number of register spills. Figure 1 1 shows an example from [MPSR95] of such tradeo . On spatial architectures, instruction scheduling is even more complicated. Examples of spatial architectures include clustered VLIWs, Raw [WTS 97] Trips [NSBK01] and ILDPs [KS02] Spatial architectures are architectures that distribute their computing resources and the register le. Communication between distant resources can incur one or more cycles of delays. On these architectures, the instruction scheduler has to partition instructions across the computing resources. ....

Ho-Seop Kim and James E. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In Proceedings of the 29th International Symposium on Computer Architecture, Anchorage, AL, May 2002.

....and the vast majority to communication infrastructure. This infrastructure is necessary precisely because superscalars do not exploit dataflow locality. It is an open question whether a Von Neumann machine can ever effectively exploit this type of locality. Aside from a few research proposals [3, 11, 12], modern processors have not tried to aggressively exploit dataflow locality. Partitioned superscalars like the Alpha 21264 and some VLIW machines [13, 14] exploit it to a limited degree, but neither is able to make full use of it. The GPA project [3] suggests that it may be possible to better ....

H.-S. Kim and J. E. Smith, "An instruction set and microarchitecture for instruction level distributed processors," in 29th International Symposium on Computer Architecture, 2002.

....instruction scheduler must somehow exploit as much ILP as possible without leading to a large number of register spills. On spatial architectures, instruction scheduling is even more complicated. Examples of spatial architectures include clustered VLIWs, Raw [24] Grid processors [22] and ILDPs [12]. Spatial architectures are architectures that distribute their computing resources. Communication between distant resources can incur one or more cycles of delays. On these architectures, the instruction scheduler has to partition instructions across the computing resources. Thus, instruction ....

H.-S. Kim and J. E. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In 29th International Symposium on Computer Architecture (ISCA), pages 71-81, 2002.

No context found.

Ho-Seop Kim, James E. Smith, "An Instruction Set and Microarchitecture for Instruction-Level Distributed Processing, International Symposium on Computer Architecture, pp. 71-81, Jun. 2002.

No context found.

Ho-Seop Kim and James E. Smith, "An Instruction Set and Microarchitecture for Instruction-Level Distributed Processing," Proc. 29 Int. Symp. Computer Architecture, 2002.

....previous VLIW based dynamic binary translator. 1 Introduction A promising paradigm for processor development is the co design of an instruction set architecture (ISA) a microarchitecture, and a dynamic binary translation system that cooperatively support an existing (virtual) ISA. Our research [16,26] is targeted at one such codesigned virtual machine (VM) that provides high performance by using a simple, distributed superscalar processor that tolerates increasing on chip wire delays and is amenable to a very high clock frequency. A key element of co designed VMs is dynamic binary translation ....

....virtual ISA (V ISA) to the implementation ISA (I ISA) This paper studies several aspects of our evolving co designed VM, with emphasis on the dynamic binary translation system. In our research, we use the Compaq Alpha instruction set as the V ISA, and an accumulator oriented instruction set [16] as the I ISA. Fig. 1 illustrates the overall codesigned VM we are studying. The following two subsections provide an overview. 1.1 Instruction Level Distributed Processing A microarchitecture trend is toward distributed, modular designs, containing partitioned issue buffers and clusters of ....

[Article contains additional citation context not shown here]

Ho-Seop Kim and James E. Smith, "An Instruction Set and Microarchitecture for Instruction-Level Distributed Processing," Proc. 29 Int. Symp. Computer Architecture, 2002.

No context found.

Ho-Seop Kim and James E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In Proceedings of the 29th Annual International symposium on Computer architecture, pages 71--81. IEEE Computer Society, 2002.

No context found.

H.-S. Kim and J. E. Smith, "An instruction set and microarchitecture for instruction level distributed processors," in International Symposium on Computer Architecture, 2002.

No context found.

H.-S. Kim and J. E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In ISCA, Alaska, May 2002.

No context found.

H.-S. Kim and J. E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In ISCA, Alaska, May 2002.

No context found.

H.-S. Kim and J. E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In ISCA, Alaska, May 2002.

No context found.

H.-S. Kim and J. E. Smith. An instruction set and microarchitecture for instruction level distributed processing. In ISCA, Alaska, May 2002.

No context found.

H. Kim and J. Smith. An instruction set and microarchitecture for instruction level distributed processing. In Proc. of the 29th Annual Int'l Symp. on Computer Architecture, May 2002. pp. 71-81.

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC