K. Gharachorloo, M. Sharma, S. Steely and S. V. Doren. "Architecture and Design of AlphaServer GS320". Proc. of International Conference on Architectural Support for Programming Language and Operating Systems, pp. 13-- 24, November 2000. Home/Search Document Not in Database Summary Related Articles Check |
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Improving Transaction Processing using a Hierarchical.. - Rubio, Valluri, John (2002) (Correct)
....3.2, to be performed in parallel by a group of computers connected with a fast interconnect network. Clusters that exist now are fiat clusters with an interconnection network. At best, the interconnection network is hierarchical (e.g. the hierarchical switch in the Compaq Alphaserver GS320 system [39, 40]) Our proposal consists of a hierarchical computational environment, not only a hierarchical interconnection network. Memik, et al. 23, 24] evaluated the performance of smart disk clusters against traditional clusters. Smart disk clusters are seen to outperform traditional cluster ....
K. Gharachorloo, M. Sharma, S. Steely, and S. V. Doren, "Architecture and design of AlphaServer GS320," in Proceedings of the Ninth International Conference on Architectural Support for Programming Languages and Operating Systems, (Boston, MA, USA), pp. 13-24, Nov. 13-15 2000.
Owner Prediction for Accelerating Cache-to-Cache.. - Acacio, Gonzalez, .. (2002) (2 citations) (Correct)
....to justify their complexity. Thus, there are compelling reasons to examine transparent hardware optimizations. Several recent research results identify cache to cache transfer misses (also known as 3 hop misses) to account for more than 60 of the total L2 miss rate in some cases [2] 3][7][13] 24] In most cases, cache to cache transfer misses occur when the home node has a stale copy of a certain memory line and the most recent copy is dirty in the cache of the processor last wrote it (the owner node) In this situation, as illustrated in Figure 1, the home directory observes the ....
....is not constrained to any network topol Address based stands for predictors whose table is accessed using the effective memory address. ogy and it is equally applicable to reduce the latency of cache to cache transfer misses caused by load and store instructions. The Compaq AlphaServer GS320 [7] constitutes an example of cc NUMA architecture specifically targeted at medium scale multiprocessing (up to 64 processors) The hierarchical nature of its design and its limited scale make it feasible to use simple interconnects, such as a crossbar switch, to connect the handful of nodes, ....
K. Gharachorloo, M. Sharma, S. Steely and S. V. Doren. "Architecture and Design of AlphaServer GS320". Proc. of International Conference on Architectural Support for Programming Language and Operating Systems (ASPLOS IX), pp. 13--24, November 2000.
The Use of Prediction for Accelerating Upgrade Misses in.. - Multiprocessors Manuel.. (Correct)
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K. Gharachorloo, M. Sharma, S. Steely and S. V. Doren. "Architecture and Design of AlphaServer GS320". Proc. of International Conference on Architectural Support for Programming Language and Operating Systems, pp. 13-- 24, November 2000.
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