Pastor, E., Cortadella, J., Kondratyev, A., Roig, O.: Structural Methods for the Synthesis of Speed Independent Circuits, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 17(11), 1998, 1108--1129.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....circuits [2] These synthesis techniques in [1, 2] have the state explosion problem because they are based on a state graph. To avoid the problem, this paper presents a direct synthesis method which does not use a state graph. Such direct methods have been proposed for speed independent circuits [3]. The method in [3] synthesizes speed independent circuits by using a structural analysis directly on signal transition graphs. In contrast, our method synthesizes timed circuits by using the relations between signal transitions. In order to synthesize timed circuits directly, timing analysis must ....

....synthesis techniques in [1, 2] have the state explosion problem because they are based on a state graph. To avoid the problem, this paper presents a direct synthesis method which does not use a state graph. Such direct methods have been proposed for speed independent circuits [3] The method in [3] synthesizes speed independent circuits by using a structural analysis directly on signal transition graphs. In contrast, our method synthesizes timed circuits by using the relations between signal transitions. In order to synthesize timed circuits directly, timing analysis must be used on the ....

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig, "Structural Methods for the Synthesis of Speed-Independent Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, pp. 1108-1129, Nov. 1998.

....be more efficient in area and speed than speedindependent circuits [6] The synthesis techniques in [1, 2, 3, 4, 5, 6] have the state explosion problem because they are based on a state graph. To overcome the state explosion problem, direct methods have been proposed for speed independent circuits [7, 8, 9, 10]. The method in [7] approximates a set of states as a cube by using a concurrency relation between transitions of the specification. It then finds an initial approximation of the implementation using these cubes. If this approximation does not satisfy correctness criteria, then iterative ....

....speed than speedindependent circuits [6] The synthesis techniques in [1, 2, 3, 4, 5, 6] have the state explosion problem because they are based on a state graph. To overcome the state explosion problem, direct methods have been proposed for speed independent circuits [7, 8, 9, 10] The method in [7] approximates a set of states as a cube by using a concurrency relation between transitions of the specification. It then finds an initial approximation of the implementation using these cubes. If this approximation does not satisfy correctness criteria, then iterative refinement is performed ....

[Article contains additional citation context not shown here]

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig, "Structural Methods for the Synthesis of SpeedIndependent Circuits", IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, Vol. 17, No. 11, pp. 1108-1129, Nov. 1998.

No context found.

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural methods for the synthesis of speed-independent circuits. IEEE Transactions on Computer-Aided Design, 17(11):1108--1129, November 1998.

....equation of an SR latch. Synthesis can be performed directly from the STG as well. These methods are based on approximation techniques similar to the one discussed in Section 7.3. However, they are more complicated and we will omit them due to the lack of space. One can look for details in [43]. 35 s r q 100 110 1 1 1 1 01 00 1 011 rq s 0 1 01 11 10 0 0 1 1 1 1 0 Figure 28: Derivation of logic equations for set dominant latch The circuits for the semaphore control of the railway system with 6 and 7 sections, automatically derived using the above method (see Figures ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 { 347, Paris(France), March 1996.

....that can manipulate them without suffering from the size of the state space. Moreover, the presented transformations preserve the structural properties of the specification, thus enabling the use of logic synthesis techniques that do not require an explicit representation of the state space [26]. The paper is organized as follows. Section 2 describes previous and related work. Section 3 presents basic definitions and background used along the paper. The encoding method and its properties is presented in Section 4. The property preserving transformations are described in Section 5. ....

.... STGs [29] However, most of them only work for marked graphs, a very restrictive class of specifications that cannot model choice behaviors [14] To the best of our knowledge, the only work in this area that has covered the synthesis of specifications with Free choice Petri nets was presented in [26]. Besides allowing the specification of choice, Free choice Petri nets also have nice structural properties that enable the use of polynomial algorithms to analyze their behavior [11] Unfortunately, none of the methods mentioned before has been able to effectively tackle the problem of finding an ....

[Article contains additional citation context not shown here]

Pastor, E., Cortadella, J., Kondratyev, A., Roig, O.: Structural Methods for the Synthesis of SpeedIndependent Circuits, IEEE Transactions on Computer-Aided Design, 17(11), November 1998, 1108--1129.

....ASTI and HADES) ESPRIT ACiD WG Nr.21949 representation of the binary encoded states [3] but does not remove the root of the complexity issue. A second approach attempts to avoid construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [16] or use of PN unfoldings [11, 19] The structural method of [16] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [4] The attempt ....

....the binary encoded states [3] but does not remove the root of the complexity issue. A second approach attempts to avoid construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [16] or use of PN unfoldings [11, 19] The structural method of [16] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [4] The attempt to generalise it within the framework of unfolding presented in ....

[Article contains additional citation context not shown here]

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....CICYT TIC 95 0419, EPSRC GR L24038 K70175 (projects ASTI and HADES) of the binary encoded states [2] but does not remove the root of the complexity issue. The second approach avoids construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [15] or use of PN unfoldings [10, 18] The structural method of [15] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [3] The ....

....of the binary encoded states [2] but does not remove the root of the complexity issue. The second approach avoids construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [15] or use of PN unfoldings [10, 18] The structural method of [15] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [3] The attempt to generalise it within the framework of unfolding presented ....

[Article contains additional citation context not shown here]

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speedindependent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....also affect the work of [1, 2] The idea of complete resynthesis of a circuit every time a new signal is inserted is exploited in [12] for the technology mapping of timed asynchronous circuits. However the search space for decomposition is again limited by a single signal network. In [13] a method for technology mapping of speedindependent circuits using complex gates was presented. This method however only identifies when a set of simple logic gates can be implemented as a complex gate, but cannot perform a speed independent decomposition of a signal function in case it does ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speedindependent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....5. Implementations with 2 input gates Restrict the specification to a certain class of Petri nets, e.g. Free choice Petri nets [11] and use structural methods that can manipulate the state space by only analyzing the underlying graph of the net and without explicitly generating the states [33]. Techniques for the efficient calculation of concurrency relations are crucial in this context [21] Annotate timing on the events, e.g. min max firing delays, and calculate the reduced state space reachable only under the specified timing constraints. This is the approach used for the ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. IEEE Transactions on Computer-Aided Design, 17(11):1108--1129, November 1998.

....In the rest of this paper, we describe the conditions to determine how the aforementioned covers can be iteratively improved and when the reached accuracy is sufficient to be considered correct. V. STG STRUCTURAL ANALYSIS This section presents structural methods for analyzing STG s [28]. This method will be used in Section VI to find approximate covers for ER s and QR s. ER s and QR s will be approximated by a much simpler region that characterizes the markings in which a given place is marked, the so called marked region. The goal of this section is to derive a single cube ....

.... an analysis of both the excitation and quiescent regions in order to check the synthesis conditions introduced in Section III (correctness and monotonicity) This section discusses a conservative technique to structurally approximate signal regions by using the marked regions of places in the STG [28]. Each signalregion approximation consists of two elements: 1) its domain in the STG, consisting of corresponding sets of places and transitions, and 2) a cover associated to each node in the domain, denoted cover function . However, the approximation based on concurrency relations is imprecise; ....

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig, "Structural methods for the synthesis of speed-independent circuits," in Proc. Eur. Design Test Conf. (EDAC-ETC.-EuroASIC), Paris, France, Mar. 1996, pp. 340--347.

....equation of an SR latch. 18 Synthesis can be performed directly from the STG as well. These methods are based on approximation techniques similar to the one discussed in Section 7.3. However, they are more complicated and we will omit them due to the lack of space. One can look for details in [43]. 35 s r q a) 0 00 100 110 1 1 1 1 01 00 1 011 0 1 0 00 rq s 0 1 01 11 10 0 0 1 1 1 1 0 1 b) Figure 28: Derivation of logic equations for set dominant latch The circuits for the semaphore control of the railway system with 6 and 7 sections, automatically derived using ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....can be achieved by deriving a hazard free twolevel sum of products [14] and obtaining a multilevel form by hazard nonincreasing transformations [18] However, these transformations cannot be generally applied for the decomposition of speed independent circuits without introducing new hazards. In [15], technology mapping for speed independent circuits is done by merely identifying sets of simple logic gates that can be implemented as a complex gate, but no logic decomposition is performed when a function cannot be implemented as a complex gate. In our present work, we are considering a more ....

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig, "Structural methods for the synthesis of speed-independent circuits," IEEE Trans. Computer-Aided Design, vol. 17, pp. 1108--1129, Nov. 1998

....can be achieved by deriving a hazard free twolevel sum of products [14] and obtaining a multi level form by hazard preserving transformations [18] However, these transformations cannot be generally applied for the decomposition of speed independent circuits without introducing new hazards. In [15], technology mapping for speed independent circuits is done by merely identifying sets of simple logic gates that can be implemented as a complex gate, but no logic decomposition is performed when a function cannot be implemented as a complex gate. In our present work we are considering a more ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 - 347, Paris(France), March 1996.

....Previous methods based on the explicit enumeration of the reachable markings for logic synthesis [12] suffer from the state explosion problem due to the arbitrary interleaving of concurrent transitions. On the other side, unfolding methods for verification [17] and structural methods for synthesis [19] suffer from lack of flexibility and generality. 2 By using boolean manipulation techniques, both logic synthesis and verification of asynchronous circuits can be comprised in a unique and fairly general environment. The utilization of BDDs provides algorithms which are computationally capable ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETCEuroASIC) , pages 340--347, Paris(France), March 1996.

....for any delays attached to their gate outputs. proach) 3] uses Binary Decision Diagrams (BDDs) to represent the state space. The SG based methods suffer from the state explosion, i.e. the number of reachable states grows exponentially with the size of the specification. The structural method of [10] uses State Machine (SM) decompositions to find an implementation avoiding the state exploration. Although it demonstrated impressive results, it is restricted to free choice specifications. Partial order techniques have also been applied in the synthesis process. Change Diagrams were introduced ....

....instances within a structural fragment of the segment. An exact approach, producing implementations comparable with those of the SG approach, is given. To overcome the state explosion problem, an approximation method based on temporal relations found in the segment is suggested. However, unlike [10], our approach uses local dependency information available for each instance of every signal transition. Only instances of signal transitions which are concurrent to a particular instance are considered for it. This gives a more accurate initial approximation and a more precise refinement. We ....

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference, pages 340--347, Paris(France), March 1996.

....have potentially low power consumption, high degree of modularity, and can be designed for average case rather than for worst case performance. Major research efforts in the asynchronous field have been devoted to solve the problems of automatic synthesis [Chu87, Ebe89, Mar90b, Lav92, vB93, PCKR96] and verification [Dil89, BMB93, McM93, BCL 94, RCP95] of circuits using high level specifications. Both problems are of special difficulty due to the necessity of considering hazards and races carefully. On the other hand, little attention has been paid to techniques for efficiently verify ....

....primary inputs. The observability of a circuit is the ability to determine the value at any node in the circuit by observing the primary outputs while controlling the primary inputs. 1 STGs and Petri nets, are a common formalism in specifying asynchronous circuits [Chu87, Lav92, YLSV92, RCP95, PCKR96] The testability of a circuit is a measure that attempts to reflect the ease with which a circuit can be tested. A circuit with high testability generally has a high degree of controllability and observability. 2.1 Definition 2.2 (Failure, Fault) A failure in a circuit occurs when the circuit ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETC-EuroASIC), pages 340--347, Paris(France), March 1996.

....conditions that apply for the particular selected architecture. This section reviews the basic notions and concepts on the monotony condition proposed in [11, 13] These implementability conditions are reformulated to be efficiently applied for the synthesis from STG specifications as described in [24, 23]. 4.1 Implementation Architecture The synthesis of SI circuits proposed in this work assume a two level Sum of Functions (SOF) architecture using a Muller s C element as memory element. A signal network N a is created for each output signal a using the following pattern: 1. Transitions for ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speedindependent circuits. In Proc. European Design and Test Conference (EDAC-ETC-EuroASIC), Paris(France), March 1996.

....of an STG can be analyzed by using the CR of the STG. A signal a and node u j are said to be concurrent ( a; u j ) 2 SCR) if exists a transition a i concurrent to u j ( a i ; u j ) 2 CR) The overall proposed synthesis cycle has a polynomial complexity except for the CR relation computation [11]. Polynomial time algorithms to compute the CR relation for live and safe FC PNs are presented in [9] while other techniques can be used to extend the synthesis process to more general classes of STG. Table 1 depicts the SCR relation for Figure 3. Concurrent pairs are denoted co. Specially note ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. EDAC-ETC-EuroASIC, March 1996. To appear.

....ASTI and HADES) ESPRIT ACiD WG Nr.21949 representation of the binary encoded states [3] but does not remove the root of the complexity issue. A second approach attempts to avoid construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [16] or use of PN unfoldings [11, 19] The structural method of [16] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [4] The attempt ....

....the binary encoded states [3] but does not remove the root of the complexity issue. A second approach attempts to avoid construction of the full reachable state space; it includes techniques either based on structural analysis of STGs [16] or use of PN unfoldings [11, 19] The structural method of [16] has given rise to the idea of an approximation based synthesis of the logic implementation of an STG. Albeit efficient in many practical cases, it is restricted to only handling a sub class of PNs free choice nets [4] The attempt to generalise it within the framework of unfolding presented in ....

[Article contains additional citation context not shown here]

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....synthesise circuits from larger descriptions. Forcage, on the other hand, uses Change Diagrams (partial order model) to derive an implementation but is restricted to specifications without choice. Construction of SG hits available computational limits due to state explosion. A structural method in [8] can implement STGs avoiding exhaustive state exploration. It uses concurrency relation between transitions of the STG to obtain an initial approximation of the implementation. If this approximation does not satisfy correctness criteria, then iterative refinement is performed, where the procedure ....

....this method has a drawback, it is restricted to free choice specifications. The main goal of this work is to develop a method for implementing STGs that cannot be synthesised by the above techniques due to the large size of their SG. A way to achieve this goal will be analogous to the one in [8] it will draw upon relations at the event based, rather This work was supported in part by the SERC grant No. GR J 52327 and ESPRIT ACiD WG Nr.21949. Collaboration between University of Newcastle and Universitat Polit echnica de Catalunya was supported by British Spanish joint research ....

[Article contains additional citation context not shown here]

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETC-EuroASIC), pages 340--347, Paris(France), March 1996.

....Previous methods based on the explicit enumeration of the reachable markings for logic synthesis [12] suffer from the state explosion problem due to the arbitrary interleaving of concurrent transitions. On the other side, unfolding methods for verification [17] and structural methods for synthesis [19] suffer from lack of flexibility and generality. By using boolean manipulation techniques, both logic synthesis and verification of asynchronous circuits can be comprised in a unique and fairly general environment. The utilization of BDDs provides algorithms which are computationally capable of ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETCEuroASIC) , pages 340--347, Paris(France), March 1996.

....correctness issues. It does not describe how to use the efficient correctness checks in an optimization loop, and does not allow the sharing of a decomposed gate by different signal networks. The latter issues were successfully resolved in [7] but only within a standard architecture approach. In [15, 13] methods for technology mapping of fundamental mode and speed independent circuits using complex gates were presented. These methods however only identify when a set of simple logic gates can be implemented as a complex gate, but cannot perform a speed independent decomposition of a signal ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....of the method. This work is, in our opinion, a big step in the right direction, but addresses mainly correctness issues. It does not describe how to use the efficient correctness checks in an optimization loop, and does not allow the sharing of a decomposed gate by different signal networks. In [14, 12] methods for technology mapping of fundamental mode and speed independent circuits using complex gates were presented. These methods however only identify when a set of simple logic gates can be implemented as a complex gate, but cannot perform a speed independent decomposition of a signal ....

....using complex gates were presented. These methods however only identify when a set of simple logic gates can be implemented as a complex gate, but cannot perform a speed independent decomposition of a signal function in case it does not fit into a single gate. A BDD based implementation of [12] is used after decomposition as a postoptimization step in this work. In our present work we are considering a more general framework which allows use of arbitrary gates and latches available in the library to decompose a complex gate function, as shown in Figure 1. In that respect, we are ....

Enric Pastor, Jordi Cortadella, Alex Kondratyev, and Oriol Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. of European Design and Test Conference, pages 340 -- 347, Paris(France), March 1996.

....synthesise circuits from larger descriptions. Forcage, on the other hand, uses Change Diagrams (partial order model) to derive an implementation but is restricted to specifications without choice. Construction of SG hits available computational limits due to state explosion. A structural method in [6] can implement STGs avoiding exhaustive state exploration. It uses concurrency relation between transitions of the STG to obtain an initial approximation of the implementation. If this approximation does not satisfy correctness criteria, then iterative refinement is performed using State Machine ....

....powerful, this method it is restricted to SM decomposable specifications. The main goal of this work is to develop a method for implementing STGs that cannot be synthesised by the above techniques due to the large size of their SG. A way to achieve this goal will be analogous to the one in [6] it will draw upon relations at the event based, rather than state based, description level. This method will, however, be free from the limitations of [6] The solution to this problem is found in the use of a partial order approach, already known to have given positive results in STG ....

[Article contains additional citation context not shown here]

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETCEuroASIC) , pages 340--347, Paris(France), March 1996.

....Due to implicit representation of the SG this tool is efficient in synthesising moderate sized examples. As all these methods work with the full SG, they suffer from state explosion, i.e. the number of reachable states grows exponentially with the size of specification. The structural method of [14] uses State Machine (SM) decompositions of STGs to obtain concurrency relations between signal transitions. Using these relations, this method finds an implementation avoiding the state exploration. Thus it demonstrated impressive results although it is restricted to free choice specifications. ....

....with those of the SG approach, is given. Although it benefits from STG unfolding segment localisation, the exact approach may still suffer from state explosion. To overcome this problem, an approximation method based on temporal relations found in the segment is suggested. However, unlike [14], our approach works with partial order representation of a fragment of system s execution. Therefore, it uses local dependency information available for each instance of every signal transition. Only instances of signal transitions which are concurrent to a particular instance are considered for ....

[Article contains additional citation context not shown here]

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural methods for the synthesis of speed-independent circuits. In Proc. European Design and Test Conference (EDAC-ETCEuroASIC) , pages 340--347, Paris(France), March 1996.

No context found.

Pastor, E., Cortadella, J., Kondratyev, A., Roig, O.: Structural Methods for the Synthesis of Speed Independent Circuits, IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 17(11), 1998, 1108--1129.

No context found.

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural Methods for the Synthesis of Speed Independent Circuits. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 17:11, 1108--1129, 1998.

No context found.

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig. Structural Methods for the Synthesis of Speed Independent Circuits. IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, 17:11, 1108--1129, 1998.

No context found.

E. Pastor, J. Cortadella, A. Kondratyev, and O. Roig, \Structural Methods for the Synthesis of Speed-Independent Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 11, pp. 1108-1129, Nov. 1998.

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