A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanvekbergen, and A. Yakovlev, \Basic Gate Implementation of Speed-independent Circuits", In Proceedings of Design Automation Conference, pp. 56-62 June, 1994.  Home/Search   Document Not in Database   Summary   Related Articles   Check

.... delay model and allowing isochronic forks 2, prac tical quasi delay insensitive circuits can be built using simple logic gates [3] A further relaxation leads to ,yeed independent circuits, which operate correctly regardless of gate delays, while wire delays are assumed to be negligible [1, 12, 20]. Both quasi delay insensitive and speed independent circuits assume that the designer is able to control wire delays, and, therefore, do not appear as interesting alternatives when moving to DSM implementations. Instead, a methodology based on assembling complex modules which are externally ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56 62, June 1994.

.... delay model and allowing isochronic forks 2 , practical quasi delay insensitive circuits can be built using simple logic gates [3] A further relaxation leads to speed independent circuits, which operate correctly regardless of gate delays, while wire delays are assumed to be negligible [1, 12, 20]. Both quasi delay insensitive and speed independent circuits assume that the designer is able to control wire delays, and, therefore, do not appear as interesting alternatives when moving to DSM implementations. Instead, a methodology based on assembling complex modules which are externally ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56--62, June 1994.

....(SI) circuit is one which assumes that gate de lays are unbounded but wires have negligible delay compared to gates. SI circuits were pioneered by Muller (see [75] and subsequently, there has been significant work both on the theoretical and practical aspects of SI and QDI circuits [32, 6, 55, 25, 74, 90, 67]. The advantage of QDI and SI circuits over DI circuits is that they can be technology mapped to libraries of basic gates like AND, OR, NAND, NOR, etc. However, the circuits must be carefully laid out so that the isochronic fork assumption or zero wire delay assumption is met. A large number of ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Ba- sic gate implementation of speed-independent circuits. In Proceedings of the 31st ACM/IEEE Design Automation Conference, 1994.

.... model and allowing isochronic forks 1 , practical quasi delay insensitive circuits can be built using simple logic gates [24] A further relaxation leads to speed independent circuits, which operate correctly regardless of gate delays, while wire delays are assumed to be negligible [25] 26] [27]. Back in 1985, Van de Sneupschet observed that the decreasing feature size of VLSI devices would have lead to a decrease of the propagation speed of electrical signals relative to the switching speed , and proposed the use of suitable commu1 A bounded skew is allowed between the di#erent ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. of the Design Automation Conf., June 1994, pp. 56--62.

....(SI) circuit is one which assumes that gate delays are unbounded but wires have negligible delay compared to gates. SI circuits were pioneered by Muller (see [75] and subsequently, there has been significant work both on the theoretical and practical aspects of SI and QDI circuits [32, 6, 55, 25, 74, 90, 67]. The advantage of QDI and SI circuits over DI circuits is that they can be technology mapped to libraries of basic gates like AND, OR, NAND, NOR, etc. However, the circuits must be carefully laid out so that the isochronic fork assumption or zero wire delay assumption is met. A large number of ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the 31st ACM/IEEE Design Automation Conference, 1994.

....or equivalently, the flow table of the circuit. But this property may be lost when logical equations and a corresponding logic diagram are derived from the flow table. It can be shown [4] that this is the case, in particular, with previously published methods based on signal transition graphs [1, 2, 3]. The method we propose also starts from a signal transition graph (STG) The key operation is to modify this STG by adding new internal variables in such a way that it gives rise to excitation functions for secondary variables which are all monotone decreasing Boolean functions, also called ....

....the design of low power and fast library cells in submicron technologies for which it is very difficult to perform a transistor sizing if the cell presents a critical race that has to be controlled. Furthermore, the resulting circuits contain less transistors than those produced by other methods [1, 2, 3, 5]. Switching activity is also reduced, as the switching between two stable states is performed by a minimal number of variables without clock inverter. The proposed method is therefore the key for the design of low power library cells. ....

A. Kondratyev et al. "Basic Gate Implementation of Speed-Independent Circuits", 31st Design Automation Conf. DAC, 1994, pp. 56-62.

.... delay model and allowing isochronic forks 2 , practical quasi delay insensitive circuits can be built using simple logic gates [3] A further relaxation leads to speed independent circuits, which operate correctly regardless of gate delays, while wire delays are assumed to be negligible [1, 12, 20]. Both quasidelay insensitive and speed independent circuits assume that the designer is able to control wire delays, and, therefore, do not appear as interesting alternatives when moving to DSM implementations. Instead, a methodology based on assembling complex modules which are externally ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56--62, June 1994.

....meet somewhat stricter timing constraints (fundamental mode assumption [64] which in practice are often easily met) but allow greater flexibility in the synthesis path. A number of tools have been developed for both burst mode [57] 65] 66] 67] 59] 68] and STG [69] 60] 70] 71] [72], 73] synthesis; these have been applied to a number of real world designs [74] 13] 8] 75] 73] 76] An alternative approach has also been proposed, called timed circuits [77] which incorporates user specified timing information to optimize the circuits. Compiling asynchronous circuits ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proceedings of the 31st ACM/IEEE Design Automation Conference. June 1994, pp. 56--62, ACM.

....or equivalently, the flow table of the circuit. But this property may be lost when logical equations and a corresponding logic diagram are derived from the flow table. It can be shown [4] that this is the case, in particular, with previously published methods based on signal transition graphs [1, 2, 3]. Page 2 The method we propose also starts from a signal transition graph (STG) The key operation is to modify this STG by adding new internal variables in such a way that it gives rise to excitation functions for secondary variables which are all monotone decreasing boolean functions, also ....

....the design of low power and fast library cells in submicron technologies for which it is very difficult to perform a transistor sizing if the cell presents a critical race that has to be controlled. Furthermore, the resulting circuits contain less transistors than those produced by other methods [1, 2, 3, 5]. Switching activity is also reduced, as the switching between two stable states is performed by a minimal number of variables without clock inverter. The proposed method is therefore the key for the design of low power library cells. Page 23 ....

A. Kondratyev et al. "Basic Gate Implementation of Speed-Independent Circuits", 31st Design Automation Conf. DAC, 1994, pp. 56-62.

....to a Sum of Products (SOP) architecture, allowing input choices and applying some optimizations to the derived circuits. Beerel s technique does not use a set of necessary conditions for synthesis, and therefore cannot guarantee to obtain a correct solution in all cases. Kondratyev et al. [9, 10] have deeply investigated the synthesis problem for the SOP architecture, defining a set of sufficient conditions to decide when a speed independent implementation can be derived. Both techniques impose two conditions that restrict the number of system specifications that can be implemented and ....

....code, i.e. 8s; s 0 2 S : s 6= s 0 ) s) 6= s 0 ) 2.21 9 R( T ) R( T ) N f f f f f S C R( T ) 1 2 R Figure 1: Signal network in a SOF architecture for signal f . 3 Implementation Architecture Overview The implementation strategy assumed in this paper resembles those proposed in [4, 3, 9, 10, 24]. Basically, the implemented network for each output signal is a two level Sum of Functions network, called a SOF architecture for short, that uses Muller s C elements as restoring elements. The C element is a two input asynchronous memory element defined by the next state equation C = AB (A ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, 1994.

....and finding a shortest path in the graph. In examples with large state This research is supported by a grant from Intel Corporation, an NSF CAREER award MIP 9625014, and a post doctoral fellowship from the Korea Science and Engineering Foundation. reqack req ack rdygo q rdy [20,50] [0,5] [0,5] 0,5] 20,50] 20,50] 20,50] go q [0,5] 0,5] 0,5] 0,5] 0,5] 0,5] 0,5] Figure 1: The timed STG for a SCSI controller. spaces, we demonstrate significant reductions in synthesis time as compared to previous methods. 2 Timed Specifications Figure 1 shows a timed deterministic signal ....

....finding a shortest path in the graph. In examples with large state This research is supported by a grant from Intel Corporation, an NSF CAREER award MIP 9625014, and a post doctoral fellowship from the Korea Science and Engineering Foundation. reqack req ack rdygo q rdy [20,50] 0,5] [0,5] [0,5] 20,50] 20,50] 20,50] go q [0,5] 0,5] 0,5] 0,5] 0,5] 0,5] 0,5] Figure 1: The timed STG for a SCSI controller. spaces, we demonstrate significant reductions in synthesis time as compared to previous methods. 2 Timed Specifications Figure 1 shows a timed deterministic signal ....

[Article contains additional citation context not shown here]

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanvekbergen, and Yakovlev, "Basic Gate Implementation of Speed-independent Circuits", In Proceedings of Design Automation Conference, pp. 56-62 Jun. 1994.

....The interval network for the interval u 7 u must satisfy the following requirements: i) it is turned on when u is enabled, ii) it is turned off before u is enabled, and (iii) once it is turned off, it remains off until u is enabled again. These requirements are the same as those in [3, 11]. The synthesis algorithm consists of four steps. First, it detects and removes redundant arcs from the specification. Second, it finds the timing relations between any two signal transitions. Third, it constructs a precedence graph for each output transition, finds all the paths in the graph, and ....

....q always occurs before go . So, q timed causes go . 3.3 Finding a Single Cube Network In this step, the synthesis procedure synthesizes each interval network as a single cube. In [3] conditions are developed in which each interval can be implemented as a single cube in a hazard free manner. In [11], they showed that specifications can be transformed to satisfy these conditions by inserting new signals. The algorithm described in this paper currently only handles specifications which have a single cube implementation. If there is no single cube implementation, new signals are added and the ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanvekbergen, and Yakovlev, "Basic Gate Implementation of Speedindependent Circuits", In Proceedings of Design Automation Conference, pp. 56-62 June, 1994.

.... s 62 C(u; k) s 0 2 C(u; k) s 0 2 ER(u; k) The definition of correct covers is based on the definition given for speed independent circuits in [29] 28] Since then, other researchers have come up with similar correctness constraints for their speed independent design methodologies [30], 31] Our definition of correct covers differs slightly from the one in [29] 28] in that QS(u) does not need to be a maximal connected set of states. It is proven in the appendix that this condition is made redundant by the entrance constraint. A concern may also be raised that a quiescent ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. ACM/IEEE Design Automation Conference, June 1994, pp. 56--62.

....complexity, but may produce sub optimal results [58] 2. Boolean minimization based methods, on the other hand, derive a Boolean function for each interface output signal from the State Graph, and use various techniques and delay models in order to implement that function without hazards [15, 42, 1, 39]. Sun et al. 56] and Lin et al. 44] proposed techniques to derive asynchronous interface specifications from a description of the protocols followed by the two partners. The basic idea (as initially developed by Borriello [6] is to match the data transfer parts of the protocol (since data ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, 1994.

.... k) TC(u; k) Since only stable signals can be included, a necessary condition for our algorithm to produce an implementation is that all trigger signals be stable (i.e. EC(u; k) TC(u; k) If a trigger signal is not stable, then we must either constrain concurrency [14] add state variables [11], or use a more general algorithm [2] The enabled cubes and trigger cubes are easily found with a single pass through the state graph. Table 1 shows the enabled cubes and trigger cubes corresponding to all the excitation regions in the SEL. Table 1. Enabled cubes and trigger cubes for the SEL. ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, 1994.

....region has multiple minimal entry points. The ER for c is the set f(1RR) R1R) 11R)g. The state (RR0) however, cannot be included, because c is stable low. Therefore, no single cube will describe the entire region. A possible solution is to add state variables to change the state coding [22]. Our approach is to create a SOP block to represent this region, instead of a simple AND gate design. To accomplish this, the algorithm tests each cover BDD to see if it is identically FALSE. If this occurs, a second (or third, etc. initial cover is created, and ORed together with the ....

Kondratyev, A., Kishinevsky, M., Lin, B., Vanbekbergen, P., and Yakovlev, A. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference (June 1994), pp. 56--62.

.... totally automatic and have been proved to be efficient for moderate size descriptions [14, 13] By using lowlevel synthesis tools, logic synthesis techniques to minimize combinational and sequential circuits as well as different delay models (e.g. bounded wire delays [13] or unbounded gate delays [12]) can be considered for the same input specification of a circuit. However, many designers agree in that describing the behavior of a circuit with a Petri net is an intricate task. In this work we propose to combine both models for the synthesis of asynchronous circuits to benefit from the ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speedindependent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56--62, June 1994.

....(TS s) and to binary encoded SG s. This framework is aimed at being independent of the sort of conflicts between states to be resolved; therefore, its application to CSC conflicts is only a special case. Another application of the method may be, e.g. solving monotonous cover conflicts [2] [20], for technology mapping of speedindependent circuits. It is essential that the theory presented in this paper is based on the concept of regions in a TS. It renders an efficient framework for such transformations due to the following two major reasons. First, regions are subsets of states which ....

....or the intersection of some pre postregions of the same event. We consider these objects to be the bricks of the blocks, and we explore the space of blocks by calculating unions of bricks. Fig. 15 presents an algorithm similar to the pruning strategy commonly used in game playing applications [20]. Initially, all bricks of the TS are calculated by: 1) obtaining all minimal regions of the TS minimal regions, and 2) calculating all possible intersections of pre postregions of the same event. Since the number of pre and postregions of an event is usually small, an exhaustive generation is ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. Design Automation Conf., June 1994, pp. 56--62.

....the advantages of speed independent designs, such as their greater temporal robustness and self checking properties. Existing methods of logic synthesis for speedindependent circuits either assume that the implementation library contains and gates with unbounded fanin and free inputinversions ([1, 5, 9]) or they use non standard hazardabsorbing flip flops whose effectiveness inpractice still needs to be evaluated ( 14] Other results on the implementability of semi modular circuits without inputs using two input two output and and or gates ( 18] are only interesting from a theoretical ....

....that provided in a concrete library or technology. 2. 2 Gate level implementability without hazards Necessary and sufficient conditions for speedindependent implementation using unbounded fanin and gates (with unlimited input inversions) bounded fanin or gates and C elements were given in [1, 9]. In this work we are considering a similar basic implementation architecture, called the standard C architecture, which is described in Figure 2. The difference from previous work is that instead of unbounded fanin gates for the setand resetlogic of C elements, we will allow only ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speedindependentcircuits. In Proceedings of the DesignAutomation Conference, 1994.

....is not violated Three first steps are shown in Figure 9. 4. 4 Gate level speed independence conditions Necessary and sufficient conditions for speed independent implementation using unbounded fanin and gates (with unlimited input inversions) bounded fanin or gates and C elements were given in [19] (extending a previous result of [2] Petrify uses a basic implementation architecture, called the standard C architecture (Figure 10) Contrary to the previous tools instead of unbounded fanin gates for the first subse, petrify can search for implementable gates, that is gates which exist in the ....

....of the standard C implementation architecture is that every first level gate implements an up or down transition of the user specified signal behavior. In order to ensure speed independent operation, a number of constraints that are collectively called the monotonous poly term cover conditions ([19]) must be satisfied. In the following we will consider partitions of the set of excitation regions of a given signal a into joint excitation regions ER j (a ) The word joint here indicates that a few excitation regions can be joined together and implemented with one logic gate in the ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, pages 56--62, June 1994.

....=f s 1 g, QR#d##2# = f s 9 s 13 s 14 g,BR#d##2# =fs 1 s 10 s 11 g, QR#d## = f s 1 s 10 s 11 g,BR#d## =fs 3 s 5 s 7 s 8 s 9 s 13 s 14 g. 4 Implementability Conditions for SI The synthesis conditions for SI circuits have been exhaustively investigated by Beerel et al. 2] and Kondratyev et al. [7]. The conditions are applied to the synthesis of a two level signal network (Sum of Products) with a memory element on its output. In this work, we will use a similar architecture in which a signal network for each non input signal a is constructed in four successive steps: 1. Transitions for ....

....#T i a ## covered by R#T i a ##, 8M 0 2 QR r #T i a ## such that M 0 #tiM , M 0 is also covered by R#T i a ##, 2. 8M 2 BR r #T i a ## covered by R#T i a ##, 8M 0 2 BR r #T i a ## such that M #tiM 0 , M 0 is also covered by R#T i a ##. The main result proved in [2, 7] was the following: If all the region covers satisfy the monotonous conditions, the circuit implementation is speed independent. The main purpose of the following sections is to show how the monotonouscover conditions can be ensured for the region covers without generating the reachability ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independentcircuits. In Proc. DAC, pages 56--62, June 1994.

....is graphically represented as a directed graph with transitions denoted by their names and places by circles, where places that have only one transition in its preset and postset are usually omitted. Also, transitions of input signals are underlined. Fig. 1(a) depicts a free choice STG, taken from [19], that will be used throughout this work. The example contains input ( and output ( signals. The corresponding reachability graph of the STG is depicted in Fig. 1(b) Fig. 2 depicts three SM s that cover the STG. 1 Checking for liveness, safeness, and redundant places can be done in ....

....existence of a hazard free implementation of the behavior. In the case where all next state functions can be correctly implemented by a hazard free complex gate, the circuit is guaranteed to be SI [5] The implementability conditions of SI circuits have been exhaustively investigated in [7] 17] [19], and [22] However, it is not always possible to implement each nextstate function with one complex gate. In general, gate libraries impose constraints on the size and functionality of the logic functions that can be implemented with only one gate. This section first introduces three different ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. ACM/IEEE Design Automation Conf., June 1994, pp. 56--62.

.... circuits recent research has developed a variety of logic synthesis techniques that allow one to trade off synthesis speed (as in the case of the fast heuristics developed by [10] 11] and [12] and optimality (as in the case of the more powerful and expensive techniques developed by [13] and [14]) Even though the underlying assumption may seem at the same time pessimistic (about gates) and optimistic (about wires) recent results [15] suggest that delayaware postoptimizations may further improve the quality of the synthesized results. Moreover, delay tuning [16] and low skew routing ....

....[16] and low skew routing [17] may help satisfy the hypothesis about the low wire skew. The main problem of logic synthesis for speedindependent circuits is that they assume nonstandard implementation libraries, such as arbitrarily complex Boolean gates [18] or arbitrary fanin AND gates [13] [14]. Standard logic decomposition followed by technology mapping is not applicable here, because arbitrary decomposition of a large gate may introduce hazards [1] 4] This paper is aimed exactly at solving that problem by defining speed independence preserving decomposition of large logic gates ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev, "Basic gate implementation of speed-independent circuits," in Proc. Design Automation Conf., 1994, pp. 56--62.

....methodology described above can be applied to the main known asynchronous circuit synthesis algorithms. We basically need to show, for each case, that the logic implementation produced by the algorithm automatically satisfies the conditions of Theorem 3.1. 4. 1 Unbounded Gate delay Circuits In [6] a standard S R implementation was suggested, based on two level combinational logic and an S R flip flop (Figure 2) where each and gate implements a region function consisting of a single cube. Each region function S a (i) and R a (i) corresponds to one rising or falling transition of signal a ....

....combinational logic and an S R flip flop (Figure 2) where each and gate implements a region function consisting of a single cube. Each region function S a (i) and R a (i) corresponds to one rising or falling transition of signal a in the initial specification of the circuit. It was proved in [6] that if each region function S a (i) and R a (i) obeys the monotonous cover requirement, then the standard S R implementation is semi modular. For any semi modular circuit C 1 we can always derive an equivalent semi modular standard S R implementation C 2 [6] Here by equivalence we mean ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speedindependent circuits. In Proceedings of the Design Automation Conference, 1994.

....These approaches can be divided according to the library of elements used in implementations. For example, 5, 1] use a memory latch for each signal and a network of gates to drive it. Early methods, e.g. 2] assume that each signal is implemented as a single complex gate. Later techniques, e.g. [16, 6], attempt to decompose the complex gates preserving the speed independence 1 of the circuit. Two primary approaches exist to date: State Graph (SG) based and structural methods. The first approach constructs a SG and extracts subsets of states required for implementation. This method is used in ....

....i ) Delta COff (a i ) DC set. 2 A correct cover may become TRUE when its variables take values corresponding to the combinations belonging to the DC set. 2.3. Atomic Complex Gate per Excitation Function The ACGpEF architecture was suggested and studied extensively in a number of papers, e.g. [6, 1]. It assumes that a separate memory element is used to produce an output signal. The Set and Reset excitation functions for this memory element are implemented as atomic complex gates. Depending on which memory element is used, the implementations are divided into: i) Standard C element ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speedindependent circuits. In Proceedings of Design Automation Conference, pages 56--62, June 1994.

....9. b b b b b b Figure 9: From bipartition to I partition 4. 4 Gate level speed independence conditions Necessary and sufficient conditions for speed independent implementation using unbounded fanin and gates (with unlimited input inversions) bounded fanin or gates and C elements were given in [19] (extending a previous result of [2] Petrify uses a basic implementation architecture, called the standard C architecture (Figure 10) Contrary to the previous tools instead of unbounded fanin 11 N S C R( T ) 1 R( T ) 2 R R( T ) b) a) N 1 2 R( T ) R( T ) S N R( T ) R (c) Figure 10: The ....

....of the standard C implementation architecture is that every first level gate implements an up or down transition of the user specified signal behavior. In order to ensure speed independent operation, a number of constraints that are collectively called the monotonous poly term cover conditions ([19]) must be satisfied. In the following we will consider partitions of the set of excitation regions of a given signal a into joint excitation regions ER j (a ) The word joint here indicates that a few excitation regions can be joined together and implemented with one logic gate in the ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, pages 56--62, June 1994. 14

....is not violated Three first steps are shown in Fig. 9. 4. 4 Gate level speed independence conditions Necessary and sufficient conditions for speed independent implementation using unbounded fanin and gates (with unlimited input inversions) bounded fanin or gates and C elements were given in [21] (extending a previous result of [2] Petrify uses a basic implementation architecture, called 11 b b b b b b Figure 9: From bipartition to I partition the standard C architecture (Fig. 10) Contrary to the previous tools instead of unbounded fanin gates for the first level, petrify can search ....

....of the standard C implementation architecture is that every first level gate implements an up or down transition of the user specified signal behavior. In order to ensure speed independent operation, a number of constraints that are collectively called the monotonous poly term cover conditions ([21]) must be satisfied. In the following we will consider partitions of the set of excitation regions of a given signal a into joint excitation regions ER j (a ) The word joint here indicates that a few excitation regions can be joined together and implemented with one logic gate in the ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, pages 56--62, June 1994.

....Systems (TSs) and to binary encoded SGs. This framework is aimed at being independent of the sort of conflicts between states to be resolved, therefore its application to CSC conflicts is only a special case. Another application of the method may be, e.g. solving Monotonous Cover conflicts [12], for technology mapping of asynchronous circuits in the basis of simple gates (AND, OR, NAND, NOR) It is essential that the theory presented in this paper is based on the concept of regions in a TS. It renders an efficient framework for such transformations due to the two following major ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, pages 56--62, June 1994.

....exists) 3.4 Persistency Persistency was introduced by Chu [4] and Meng [19] as a necessary condition to synthesize hazard free circuits. However, Lavagno et al. 16] show that hazard free implementations can be derived even for non persistent specifications. More recently, Kondratyev et al. [10, 11] proved that persistency is in fact a necessary condition to guarantee that the states in a given excitation region can be covered with only one cube. Violations of the persistency condition can be checked by studying the concurrence between the signals in the specification. A transition a i is ....

....Figure 5, transition d =1 has one input trigger transition a =1 and one output trigger transitions b =1; additionally, transition a =1 is input non persistent to d =1. 4 Speed independence Synthesis Conditions The implementability conditions of SI circuits have been exhaustively investigated in [31, 32, 3, 2, 11, 13]. These conditions are typically applied to the synthesis of two level networks with a memory element for each output. The implementability conditions can be classified into the general necessary conditions N d R d a c b S d a a c b C N d S d R d a c b a c b C Figure 7: Two different ....

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A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56--62, June 1994.

....and of 16 reachable markings. Note that signal c2 is non persistent for r1 and r1 Gamma. Similarly, c1 is non persistent for r2 and r2 Gamma. 4 Synthesis Conditions The restrictive operating discipline to guarantee the correctness of a SI circuit requires a formal set of synthesis conditions [1, 5]. The synthesis conditions apply to the synthesis of every output signal, and follow a two level Sum of Functions (SOF) architecture with a memory element on its output. The signal network for each output signal a is constructed in three successive steps: 1. The switching of each transition a i ....

....(falling) region cover can be responsible for a rising (falling) transition of the output signal. When one rising and one falling region cover are competing to produce a transition of the output signal, the C element contains enough information to decide the correct ordering of the transitions [5]. The region cover R(a i ) may cover markings in QR(a i ) or markings in BR(a i ) under certain restrictions [12] Markings shared by several QR and BR regions of the same signal cannot be covered by any region cover. Otherwise, the one hot encoding discipline of the SOF signal network is violated ....

[Article contains additional citation context not shown here]

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. DAC, pages 56--62, June 1994.

....= f s 9 s 13 s 14 g, BR(d =2) f s 1 s 10 s 11 g, QR(d Gamma) f s 1 s 10 s 11 g, BR(d Gamma) f s 3 s 5 s 7 s 8 s 9 s 13 s 14 g. 4 Implementability Conditions for SI The synthesis conditions for SI circuits have been exhaustively investigated by Beerel et al. 2] and Kondratyev et al. [7]. The conditions are applied to the synthesis of a two level signal network (Sum of Products) with a memory element on its output. In this work, we will use a similar architecture in which a signal network for each non input signal a is constructed in four successive steps: 1. Transitions for ....

....QR r (T i a ) covered by R(T i a ) 8M 0 2 QR r (T i a ) such that M 0 [tiM , M 0 is also covered by R(T i a ) 2. 8M 2 BR r (T i a ) covered by R(T i a ) 8M 0 2 BR r (T i a ) such that M [tiM 0 , M 0 is also covered by R(T i a ) The main result proved in [2, 7] was the following: If all the region covers satisfy the monotonous conditions, the circuit implementation is speed independent. The main purpose of the following sections is to show how the monotonouscover conditions can be ensured for the region covers without generating the reachability graph ....

[Article contains additional citation context not shown here]

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independentcircuits. In Proc. DAC, pages 56--62, June 1994.

....equations for the circuit may find that some of them are far too complex to be realised in one gate. The use of input inversions may also be inadequate to the technology mapping requirements. The existing formal techniques, which again theoretically produce correct by construction decompositions [2, 9], are not quite efficient in practice, nor do they work for widest possible class of output persistent STGs. Therefore, the designer may introduce some modifications by hand; thus a check must be done whether they bring any hazards to the circuit or not. In our case, it would also be desirable to ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen and A. Yakovlev, "Basic gate implementation of speed-independent circuits,", Proc. DAC'94, San Diego, June 1994, IEEE Comp. Society Press, N.Y., pp. 56-62.

....partitioning, 2) new signal insertion, and (3) reconstruction of the model in Petri net form, based on the concept of region of states, will prove useful in solving other problems in asynchronous circuit synthesis. In particular, the technology mapping problem for Speed Independent circuits ([4]) can be cast in this form. ASSASSIN petrify benchmark states area CPU area CPU adfast 44 390 0.4 294 10.5 nak pa 56 456 0.7 456 4.8 alloc outbound 17 350 0.1 350 5.4 nowick 18 340 0.1 428 2.6 ram read sbuf 36 406 0.2 406 6.0 sbuf ram write 58 764 0.7 300 23.9 sbuf read ctl 15 244 0.0 244 1.4 ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, 1994.

....using boolean minimization techniques described, for example, in [21] There are a number of methods, either at the STG, State Graph or even logic circuit level, to map such a rather abstract design into a specific implementation architecture. We do not present them here and refer the reader to [1, 25, 21, 16, 37]. Assume that the STG model is obtained from the original labelled Petri net through a signalling expansion [47] Each signal event in the Petri net is explicitly represented by either a 0 to 1 or 1 to 0 transition of the corresponding binary variable. In order to separate the phases, thereby ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of DAC-31, pages 56--62. Computer Science Press, 1994.

....in logic decomposition and technology mapping for speed independent circuits quite specific compared to their synchronous counterparts. This work has been partially supported by ACiD WG (ESPRIT 21949) UK EPSRC project ASTI GR L24038 and CICYT TIC 95 0419 Two examples of the first category [1, 8] present initial attempts to move from complex gates to a more structured implementation. The basic circuit architecture includes C elements (acting as latches) and combinational logic, responsible for the computation of the excitation functions for the latches. This logic is assumed to consist of ....

....This logic is assumed to consist of AND gates with potentially unbounded fain and unlimited input inversions and bounded fanin OR gates. Necessary and sufficient conditions for implementability of circuits in such an architecture (called the standard C architecture) have been formulated in[8, 1]. They are called Monotonic Cover (MC) requirements. The intuitive objective of the MC conditions is to make the first level (AND) gates work in a one hot fashion with acknowledgment through one of the Celements. Following this approach, various methods for speed independent decomposition and ....

[Article contains additional citation context not shown here]

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, 1994.

....tools, have been developed for speed independent circuits over the last few years. Unfortunately, current automated synthesis techniques still suffer from a severe limitation: either they assume that the implementation library contains and gates with unbounded fanin and free input inversions ([1, 3, 9]) or they use non standard hazard absorbing flip flops This work has been partially supported by grant CICYT TIC 95 0419, by EPSRC (visiting fellowship grants GR J72486 and GR J78334, and research grant GR J52327, and MURST (project VLSI architectures ) whose effectiveness in practice ....

....be performed on them before they can be reliably used in practice. Moreover, their correct operation relies on the assumption that inverter delays are negligible with respect to and gate delays (rather than being smaller than and gate delays, as assumed by most other research work in the area [9]) This assumption is unrealistic in any currently known implementation technology that does not use dual rail signals, in which both a signal and its complement are generated and carried around. Burns, on the other hand, in [2] analyzes the correctness conditions for a decomposition of a ....

[Article contains additional citation context not shown here]

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, 1994.

....gates directly, by finding a behavior preserving interconnection of simpler gates. In both cases, the major functional issue, in addition to logic simplification, is that the decomposedlogic must not violate the original speed independent specification. Two examples of the first category are [1, 8]. The basic circuit architecture includes C elements (acting as latches) and combinational logic. This logic is assumed to consist of AND gates with potentially unbounded fain and unlimited input inversions and bounded fanin OR gates. Monotonic Cover (MC) requirements ensure implementability of a ....

....the state graph specification, and re synthesizes logic from the latter. Thus parts 1 and 2 are applied to each complex gate that cannot be mapped into the library. Finally, Part 3 does library matching to recover area and delay. This method improves significantly over previously known techniques [1, 8, 7]. This is due to the significantly larger optimization space exploited by using (1) Boolean relations for decomposition and (2) a broader class of latches 6 . Furthermore, the ability to implement sequential functions with SR and D latches significantly improves the practicality of the method. ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, 1994.

....mode is often too restrictive and in particular is not satisfied for logic implementing signal functions in synthesis using STGs. 3. 4 Decomposition and Technology Mapping One of the partial solutions to the logic decomposition for non fundamental mode, called the monotonous cover requirement [1, 14], allows one to decompose any function into two level combinational logic and a latch. This does not solve however a problem of breaking gates if the fan in or fan out is too large. The latest results [4, 5] allow one to obtain a hazard free decomposition (and then map the decomposed solution into ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of the Design Automation Conference, pages 56--62, June 1994.

....i ) Delta C Off (a i ) DC set. 2 A correct cover may become TRUE when its variables take values corresponding to the combinations belonging to the DC set. 2. 3 Atomic Complex Gate per Excitation Function The ACGpEF architecture was suggested and studied extensively in a number of papers, e.g. [2, 8, 1]. It assumes that a separate memory element is used to produce an output signal. The Set and Reset excitation functions for this memory element are implemented as atomic complex gates. Depending on which memory element is used, the implementations are divided into: i) Standard C element ....

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proceedings of ACM/IEEE Design Automation Conference, pages 56--62, June 1994.

No context found.

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanvekbergen, and A. Yakovlev, \Basic Gate Implementation of Speed-independent Circuits", In Proceedings of Design Automation Conference, pp. 56-62 June, 1994.

No context found.

, Alex Kondratyev, Michael Kishinevsky, Bill Lin, Peter Vanbekbergen, Alex Yakovlev, Basic Gate Implementation of Speed-Independent Circuits, in Proc. ACM/IEEE Design Automation Conference, pages 56-62, June 1994

No context found.

A. Kondratyev, M. Kishinevsky, B. Lin, P. Vanbekbergen, and A. Yakovlev. Basic gate implementation of speed-independent circuits. In Proc. ACM/IEEE Design Automation Conference, pages 56--62, June 1994. 29

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