E. Sprangle and D. Carmean, "Increasing Processor Performance by Implementing Deeper Pipelines," in 29th Annual International Symposium on Computer Architecture, 2002. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
First 50 documents
Microarchitecture Evaluation With Physical Planning - Jason Cong Ashok (2003) (4 citations) (Correct)
....more severe and the processor may be unable to communicate across the chip in a single cycle [1, 2] Agarwal et al. 1] predict that current processor designs will improve by at best, 12.5 per year in terms of performance over the next fourteen years due to hardware scaling concerns. Prior work [1, 3, 4] has demonstrated the need to consider both cycle time and throughput (IPC) when measuring overall processor performance. However, architects often have little or incomplete physical design information about the architectural space they are considering. Accurate area and delay information for a ....
....of the maximum latency configurations (17 32) we see a dramatic increase in BIPS for these configurations due to the cycle time we are able to achieve with the deeper pipelining. The extra data cache latencies and larger branch misprediction depth are particularly hard to tolerate, as shown in [3], and have a large impact on IPC for these configurations. This again, demonstrates the importance of examining both IPC and cycle time when exploring a design space. Ultimately, these results emphasize the importance of taking interconnect e#ects into account when exploring an architectural ....
E. Sprangle and D. Carmean, "Increasing processor performance by implementing deeper pipelines," in 29th Annual International Symposium on Computer Architecture, 2002.
Microarchitecture Evaluation With Floorplanning - And Interconnect Pipelining (Correct)
No context found.
E. Sprangle and D. Carmean, "Increasing Processor Performance by Implementing Deeper Pipelines," in 29th Annual International Symposium on Computer Architecture, 2002.
Optimizing Pipelines for Power and Performance - Viji Srinivasan David (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Architecture (ISCA-29), May 2002.
Dataflow: A Complement to Superscalar - Budiu, Artigas, Goldstein (2005) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In International Symposium on Computer Architecture (ISCA), 2002.
Piecewise Linear Branch Prediction - Daniel Jimenez Department (Correct)
No context found.
Eric Sprangle and Doug Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25--34, Anchorage, Alaska, May 2002.
Integrated Analysis of Power and Performance For.. - Zyuban, Brooks.. (2004) (Correct)
No context found.
E. Sprangle and D. Carmean, "Increasing Processor Performance by Implementing Deeper Pipelines," Proc. 29th Int'l Symp. Computer Architecture (ISCA-29), May 2002.
Prophet/Critic Hybrid Branch Prediction - Falcón, Stark, Ramirez, Lai.. (2004) (4 citations) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th Annual Intl. Symposium on Computer Architecture, pages 25--34, May 2002.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, etal. (2004) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25--34, May 2002.
Combining Hyperblocks and Exit Prediction to.. - Ranganathan.. (2002) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25--34, May 2002.
Design and Analysis of Routed Inter-ALU Networks.. - Singh.. (2003) (Correct)
No context found.
Eric Sprangle and Doug Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Archictecture, pages 25--34, May 2002.
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE.. - Nagarajan, al. (2004) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Architecture, pages 25--34, May 2002.
Routed Inter-ALU Networks for ILP Scalability and.. - Sankaralingam, Singh, .. (2003) (3 citations) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th International Symposium on Computer Archictecture, pages 25--34, May 2002.
RuDRA: A Reactive Dissipation Reducing Architecture - Rodrigues (2003) (Correct)
No context found.
Eric Sprangle and Doug Carmean. Increasing processor performance by implementing deeper pipelines. In ISCA, 2002.
Checkpoint Processing and Recovery: - Towards Scalable Large (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 25--34, May 2002.
On Reducing Register Pressure and Energy in Multiple-Banked.. - Abella, Gonzalez (Correct)
No context found.
E. Sprangle, D. Carmean. Increasing Processor Performance by Implementing Deeper Pipelines. In ISCA 2002.
Cache Implications of Aggressively Pipelined High.. - Dysart, Moore.. (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In 29th Annual International Symposium on Computer Architecture.
A Flexible Simulator of Pipelined Processors - Ben Juurlink Koen (Correct)
No context found.
Carmean Sprangle. Increasing Processor Performance by Implementing Deeper Pipelines. In Proc. 29th Annual International Symposium on Computer Architetecture(ISCA02), 2002. 493
On-Chip Wires: Scaling and Efficiency - Ho (2003) (1 citation) (Correct)
No context found.
E. Sprangle et al., "Increasing processor performance by implementing deeper pipelines," Proceedings of the 29th International Symposium on Computer Architecture, May 2002.
Performance Implications Of Future-Generation Memory Systems.. - Fertig (2003) (1 citation) (Correct)
No context found.
E. Sprangle and D. Carmean, \Increasing processor performance by implementing deeper pipelines," in Proceedings of the 29th Annual International Symposium on Computer Architecture, 2002, pp. 25-34.
On-Chip Communication Design: Roadblocks and Avenues .. - Carloni.. (2003) (1 citation) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing Processor Performance by Implementing Deeper Pipelines. In 29th Annual Intl. Symposium on Computer Architecture, pages 25--36. IEEE, May 2002.
Checkpoint Processing and Recovery: - Towards Scalable Large (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 25--34, May 2002.
Physical Register Inlining - Lipasti, Mestan, Gunadi (2004) (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In International Symposium on Computer Architecture, 2002.
Microbenchmarks for Determining Branch Predictor.. - Milenkovic, Milenkovic.. (2004) (1 citation) (Correct)
No context found.
Sprangle E, Carmean D. Increasing Processor Performance by Implementing Deeper Pipelines. In Proceedings of the 29th ISCA, 2002; 25-34.
Using Interaction Costs for Microarchitectural.. - Fields, Bodik, Hill.. (Correct)
No context found.
E. Sprangle and D. Carmean. Increasing processor performance by implementing deeper pipelines. In 29 on Computer Architecture, 2002.
L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy - Machanick, Patel (Correct)
No context found.
Eric Sprangle and Doug Carmean. Increasing processor performance by implementing deeper pipelines. In Proc. 29th Annual Int. Symp. on Computer architecture, pages 25--34, Anchorage, Alaska, 2002.
First 50 documents
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC