Andre Seznec, Stephen Felix, Venkata Krishnan, and Yiannakakis Sazeides. Design tradeoffs for the Alpha EV8 conditional branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture, May 2002. Home/Search Document Details and Download
Summary Related Articles Check |
This paper is cited in the following contexts:
Fetching Instruction Streams - Alex Ramirez Oliverio (2002) (2 citations) (Correct)
....aligned instructions in a special purpose cache. The next line and set predictor (NLS) architecture [5] implemented in the Alpha 21264 [12] also allows fetching of multiple basic blocks in a single cycle, as long as they reside sequentially in the same cache line. The Alpha EV8 architecture [34] uses an interleaved BTB and a multiple branch predictor to fetch instructions from multiple basic blocks up to the first encountered taken branch, much in the way the SEQ.3 engine described in [31] The rePLay microarchitecture [22] uses a front end derived from the trace cache, making extensive ....
....as the possible interference and prefetching effects on the instruction cache. We compare our stream fetch architecture with three other state of the art fetch architectures: the FTB architecture [30] using a perceptron branch predictor [18] the Alpha EV8 architecture using a 2bcgskew predictor [34], and the trace cache architecture using a trace predictor [32] and selective trace storage [29] Table 2 shows the values used in the processor simulation. Most of the setups correspond to the fetch engine, which was simulated in greater detail. In all cases in which the branch predictor ....
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. Proceedings of the 29th Annual Intl. Symposium on Computer Architecture, 2002.
Branch Prediction On Demand: an Energy-Efficient Solution - Chaver, Pinuel, Prieto, .. (2003) (Correct)
....Design, Experimentation, Performance Keywords Adaptive, Branch Prediction, Profiling 1. INTRODUCTION Branch prediction is a central piece of technology in exploiting instruction level parallelism. Modern high end processors use an array of tables for branch direction and target prediction [13]. These tables are quite large in size (352K bits total for the direction predictor alone in Alpha EV8) and they are accessed every cycle resulting in significant energy consumption sometimes more than 10 of the total chip power. While high accuracy is essential for high performance and energy ....
....buffer (BTB) helps provide the target address quickly. Increasing the size and associativity of BTBs helps reduce conflict and capacity misses. However, for certain applications, large structures can be a waste. For example, compress in the SPEC95 suite has only 46 static branch instructions [13]. Therefore, we propose to resize BTB on the fly. BTB is very similar to a normal data cache in terms of organization and access. There are several schemes in literature discussing how to resize caches and the circuitry to perform the resizing. The main idea of such techniques is to exploit ....
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. In International Symposium on Computer Architecture, pages 296--306, Anchorage, AK, May 2002.
Reconsidering Complex Branch Predictors - Jimenez (2003) (2 citations) (Correct)
....have become larger, more complex, and more accurate. This trend will continue into the future, with branch predictor hardware budgets running into the scores or hundreds of kilobytes. For example, the design for the Compaq EV8 included a hybrid branch predictor with approximately 45KB of state [14]. Figure 1 shows the arithmetic mean misprediction rates achieved over the SPEC 2000 integer benchmarks by extending several branch predictors from the literature into large hardware budgets, as well two very complex but highly accurate predictors: the multi component hybrid predictor [5] and the ....
....(Realistic Delay w Overriding) Perceptron (No Delay) Figure 2. Ideal IPC for perceptron and multicomponent predictors, contrasted with realistic, overriding versions nique was used for the Alpha EV6 branch predictor [9] and was built into the design for the Alpha EV8 branch predictor [14]. Because of penalties associated with their implementations, the extra accuracy provided by such complex predictors does not yield a proportionate increase in performance. To illustrate our point, Figure 2 shows the instructions per cycle (IPC) rates yielded by the multi component hybrid ....
[Article contains additional citation context not shown here]
Andre Seznec, Stephen Felix, Venkata Krishnan, and Yiannakakis Sazeides. Design tradeoffs for the Alpha EV8 conditional branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture, May 2002.
Dynamic Data Dependence Tracking and its Application to.. - Chen, Dropsho, Albonesi (Correct)
....information and the branch outcome can for some branches be stronger than either history or path information. A two level predictor using ARVI at the second level achieves a 12.6 overall IPC improvement for the SPEC95 integer benchmarks as compared to the stateof the art two level predictor [26] proposed for the Alpha EV8. The rest of this paper is organized as follows. The hardware mechanism for data dependence tracking is described in Section 2, and potential applications are reviewed in Section 3. A novel branch prediction scheme (ARVI) based on the data dependence information is ....
....f60; 80; 100g cycles initial latencies depend on pipeline length We have extended the base simulator to support two levels of branch prediction. In all configurations, the first level of branch prediction is a hybrid predictor based on the Alpha EV8 branch predictor design called 2Bc gskew [26]. There are three predictor tables and one table that controls which table provides the prediction. Each table is 1 KB in size for a total of 4 KB for the level one predictor and modeled as having single cycle access. Future technology estimates from [18] suggest that modest size predictor RAMs ....
[Article contains additional citation context not shown here]
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor. pages 295--306, May 2002.
Pointer Cache Assisted - Collins, Sair, Calder, Tullsen (2002) (Correct)
.... described in the previous section, the precomputation slices are created 7 Pipeline Structure 8 stage pipeline, 1 cycle misfetch penalty, 6 cycle minimum mispredict penalty Fetch 8 instructions total from up to two threads Branch Predictor 88kbit 2Bc gskew branch predictor modeled after the EV8 [20] branch predictor but with instantaneous global history update (which also accounts for its smaller size) 256 entry 4 way associative BTB Execution Resources 6 total int units, 4 can perform mem ops, 3 fp. All units pipelined, 256 int and 256 fp renaming regs 128 entry int and fp instruction ....
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In 29th Annual International Symposium on Computer Architecture, May 2002.
Characterization of Embedded Applications for Decoupled.. - Djabelkhir, Seznec (2003) Self-citation (Seznec) (Correct)
No context found.
Seznec, A., Felix, S., Krishnan, V., and Sazeides, Y. , Design tradeoffs for the alpha EV8 conditional branch predictor, In Proceedings of the 29th International Symposium on Computer Architecture (ISCA-02), New York, 2002, pp. 295--306.
Piecewise Linear Branch Prediction - Daniel Jimenez Department (Correct)
No context found.
Andre Seznec, Stephen Felix, Venkata Krishnan, and Yiannakakis Sazeides. Design tradeoffs for the Alpha EV8 conditional branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture, May 2002.
Control Flow Optimization Via Dynamic Reconvergence Prediction - Jamison Collins Dean (2004) (1 citation) (Correct)
No context found.
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In 29th Annual International Symposium on Computer Architecture, May 2002.
Managing Wire Delay in Large Chip-Multiprocessor Caches - Beckmann, Wood (2004) (Correct)
No context found.
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design Tradeoffs for the Alpha EV8 Conditional Branch Predictor*. 29th Annual International Symposium on Computer Architecture, May 2002.
Demand-Only Broadcast: Reducing Register File and Bypass Power - In Clustered Execution (Correct)
No context found.
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In Proceedings of the 29th Annual International Symposium on Computer Architecture, pages 295--306, 2002.
Combining Hyperblocks and Exit Prediction to.. - Ranganathan.. (2002) (Correct)
No context found.
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In Proceedings of the 29th International Symposium on Computer Architecture, pages 295--306, May 2002.
Clustered Multithreaded Architectures - Pursuing Both IPC.. - Collins, Tullsen (2004) (Correct)
No context found.
A. Seznec, S. Felix, V. Krishnan, and Y. Sazeides. Design tradeoffs for the alpha ev8 conditional branch predictor. In 29th Annual International Symposium on Computer Architecture, May 2002.
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC