| B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999. |
....it is di#cult to apply these analyses directly to sparse matrix kernels due to the presence of indirect and irregular memory access patterns. Nevertheless, there have been a number of notable modeling attempts in the sparse case. Temam and Jalby [39] Heras, et al. 20] and Fraguela, et al. [16] have developed sophisticated probabilistic cache miss models, but assume uniform distribution of non zero entries. These models vary in their ability to account for self and cross interference misses. In this study, we see that on current and future machines, whose cache sizes continue to grow, ....
....implementations approaches upper bounds on a variety of architectures, suggesting that additional gains from low level tuning (e.g. instruction scheduling) will be limited. Instead we are examining other algorithmic ways of improving reuse, for instance, via the use of multiple right hand sides [29, 16, 22]. Preliminary results on Itanium for sparse matrix multiple vector mltiplication show speedups of 6.5 to 9 over single vector code [40] Register blocking with square blocks on a uniformly aligned grid appears to be too limiting to see appreciable performance benefits. Encouraged by the gains ....
B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
....di#cult to apply these analyses directly to sparse matrix kernels due to the presence of indirect and irregular memory access patterns. Despite the di#culty of analysis in the sparse case, there have been a number of notable attempts. Temam and Jalby [29] Heras, et al. 15] and Fraguela, et al. [10] have developed sophisticated probabilistic cache miss models, but assume uniform distribution of non zero entries. These models are primarily distinguished from one another by their ability to account for self and crossinterference misses. In this study, we will see that on current and future ....
....twice. Our preliminary results indicate that we can go significantly faster, up to a factor of 2. Fourth, we can identify and tune higher level sparse kernels that also permit more matrix reuse. An example is applying register blocking to sparse matrix multiple vector multiplication (SpMM) [23, 10, 17]. This kernel can be exploited in iterative solvers with multiple right hand sides and also in block eigensolvers. On the Itanium and Ultra 2i we have observed speedups of up to 6.5 and 9 times that of SpMM with a single right hand side. Another example is computing A Ax, which is used in ....
B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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Basilio B. Fraguela, Ram on Doallo, and Emilio L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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Basilio B. Fraguela, Ram on Doallo, and Emilio L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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Basilio B. Fraguela, Ram on Doallo, and Emilio L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
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B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), 1999.
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B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), March 1999.
No context found.
B. B. Fraguela, R. Doallo, and E. L. Zapata. Memory hierarchy performance prediction for sparse blocked algorithms. Parallel Processing Letters, 9(3), 1999.
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