R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th Annual International Symposium on Microarchitecture, December 2001.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Lock Elision Steven S. Lumetta University of Illinois at Urbana Champaign, ECE and CSL, lumetta uiuc.edu The idea of executing sections of code optimistically in parallel in order to increase performance has recently regained popularity in the computer architecture literature. Two papers [6, 7] suggest the speculative elision of lock acquisitions in threaded programs to eliminate unnecessary serialization and to allow the use of more coarse grained locks without sacrificing performance. These schemes rely primarily on extensions to processor caching mechanisms, an idea introduced in ....

....programs to eliminate unnecessary serialization and to allow the use of more coarse grained locks without sacrificing performance. These schemes rely primarily on extensions to processor caching mechanisms, an idea introduced in [4] This paper suggests a minor extension to such a protocol [7] to enable production time detection and localization of synchronization errors in threaded applications. Although the idea may also apply to some earlier techniques [3] its value has not been previously recognized. The closest related work in terms of detecting synchronization errors is Eraser ....

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R. Rajwar and J. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In International Symposium on Microarchitecture, pages 294--305, 2001.

....uses processor consistency with 8 MB second level cache with 128 bytes. The third test case shows the miss rate of a system that uses processor consistency, but is somehow able to ignore serializations and does not need to enforce the ordering that the programmer specified (this is similar to [15]) In the last test case, we show the miss rate of a system with sequential consistency, 8 MB second level caches, and 512 byte lines, which had the highest performance of all the sequential consistency cases (as seen in Section 3) In the case of the Perl version of SPECweb99, we see that the ....

R. Rajwar and J. Goodman. " Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution." In Proceedings of the 34 (MICRO-34), December 2001.

....to a hardware waitthen block technique best suited for SMT. Intel [14] also discusses the need for threads on a multithreaded processor to block to the operating system, but they provide no way to combine this with efficient hardware locks. Other relevant work includes speculative lock elision [37], which improves performance by dynamically eliminating the need for many synchronization operations rather than by improving synchronization. 8 CONCLUSION In this paper, we examined how dynamic memory allocation, stack allocation and synchronization techniques affect the performance of ....

R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In 34th International Symposium on Microarchitecture, December 2001.

....calls and returns for callee saved registers by predicting that register values used by a speculative thread are those values which exist at the point the speculative thread is spawned. In other related work, Speculative Lock Elision detects and exploits temporal silence of silent store pairs [20]. In multiprocessor systems, we find that a surprising number of writes that induce communication misses are temporally silent. We find that an idealized scheme for exploiting temporal silence can remove up to 45 of sharing misses in the commercial workloads we study. Further, we propose a ....

....store pair as an atomic temporally silent store pair. We find that capturing such temporal silence by delaying writes (hence exploiting PowerPC weak ordering) is relatively ineffective, leading to a maximal 3 reduction in sharing misses. Speculative techniques for ensuring atomicity, similar to [20], could improve that result, but since this paper focuses on nonspeculative tech FIGURE 1. Extending the Lifetime of a Shared Cache Line. Lifetime is extended by avoiding writes to other parts of the word (false sharing) ignoring silent writes (update silent sharing) ignoring temporally silent ....

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R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In MICRO34, December 2001.

....the presence of access conflicts and speculative buffer overflow. This fact, plus the support for speculative barriers and flags, sets our proposal apart from lock free optimistic synchronization schemes of similar hardware simplicity, such as Transactional Memory [16] and Speculative Lock Elision [27]. In these schemes, which only apply to critical sections, the speculative mechanism by itself does not guarantee forward progress (Section 7) Speculative Synchronization requires simple hardware: one bit per line and some simple logic in the caches, plus support for register checkpointing. ....

....all changes and jumps back to the beginning of the critical section. If at the time a thread completes the critical secion no conflicts have been flagged, the thread can commit. 7.1. 2 Speculative Lock Elision Concurrently to our work [25] Rajwar and Goodman propose Speculative Lock Elision (SLE) [27]. SLE dynamically converts lockbased into lock free codes, by removing acquire and release operations in the instruction stream from the processor pipeline. As in TM, all threads execute critical sections speculatively. SLE also leverages the coherence protocol to detect conflicts. Compared to TM, ....

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R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling highly concurrent multithreaded execution. In International Symposium on Microarchitecture, pages 294--305, Austin, TX, Dec. 2001.

....to be made available[18] This can bring usability benefits to the program writer in that they can use coarser granularity locks without suffering the usual performance degradation that results. Rajwar and Goodman suggest speculative lock elision, where lock operations are speculatively eliminated[21]. The on chip write buffers are made part of the coherent state in order to allow for effectively atomic updates. 7. CONCLUSIONS paradigm to create more reliable software, and proposes an architectural design that allows the software and hardware to cooperate in making this paradigm more ....

R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Microarchitecture, December 2001.

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R. Rajwar and J.R. Goodman, Speculative Lock Elision: Enabling Highly-Concurrent Multithreaded Execution, 34th International Symposium on Microarchitecture, 2001.

....philosophy behind the solution lies in maintaining the current programming model while transparently transforming the model in hardware to a concurrent one. 23 1.4.1 Primary contributions The thesis makes two primary contributions: 1. Speculative Lock Elision. Speculative Lock Elision (SLE) [139] for the first time demonstrates that it is possible to execute and commit concurrently, critical sections protected by the same lock without acquiring (or requiring exclusive permissions on) the lock if the critical section executions do not experience any data conflict. SLE is a ....

....have no conflict. We do not have to provide special support for forward progress because, for conflicts, we simply fall back to the original code sequence, acquiring and releasing the lock in the conventional way. Hardware only lock free. To the best of our knowledge, Speculative Lock Elision [139] is the first hardware only lock free proposal that executes lock based programs in a lock free manner in the absence of data conflicts. Database optimistic concurrency control. Extensive research has been conducted in databases on concurrency control and Thomasian [161] provides a good summary ....

Ravi Rajwar and James R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In Proceedings of the 34th International Symposium on Microarchitecture, pages 294--305, December 2001.

....Removal (TLR) TLR uses modest hardware to convert lock based critical sections transparently and dynamically into lock free optimistic transactions and uses timestampbased fair conflict resolution to provide transactional semantics and starvation freedom. TLR uses Speculative Lock Elision (SLE) [30] as an enabling mechanism. SLE is a recent hardware proposal for eliding lock acquires from a dynamic execution stream, thus breaking a critical performance barrier by allowing non conflicting critical sections to execute and commit concurrently. SLE showed how lockbased critical sections can be ....

.... scope of a transaction, b) Speculatively execute the transaction without requesting or acquiring the lock, c) Use a conflict resolution scheme to order conflicting transactions, and d) Use a technique to give the appearance of an atomic commit of the transaction, such as is provided by SLE [30]. TLR performs active concurrency control to ensure correct coordinated access to the data experiencing conflicting access by using the data itself rather than locks. Unlike TLR, SLE only identifies situations where lock based concurrency control is not necessary namely the absence of data ....

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R. Rajwar and J. R. Goodman. Speculative Lock Elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th International Symposium on Microarchitecture, pages 294-- 305, Dec. 2001.

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R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th Annual International Symposium on Microarchitecture, December 2001.

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R. Rajwar and J. Goodman, "Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution", Intl. Symp. on Microarchitecture, pp. 294-305, 2001.

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R. Rajwar and J. Goodman. Speculative Lock Elision: enabling highly concurrent multithreaded execution. In MICRO 34: Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture, pages 294--305. IEEE Computer Society, 2001.

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R. Rajwar and J. R. Goodman. Speculative lock elision: enabling highly concurrent multithreaded execution. In MICRO 34: Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture, pages 294--305. IEEE Computer Society, 2001.

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R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In Proceedings of the 34th Int. Symp. on Microarchitecture, pages 294--305, Dec. 2001.

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R. Rajwar and J.R. Goodman, "Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution," Proc. 34th Int'l Symp. Microarchitecture, IEEE CS Press, 2001, pp. 294-305.

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R. Rajwar and J.R. Goodman, "Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution," 34th Int'l Symp. Microarchitecture (MICRO-34), IEEE CS Press, Dec. 2001, pp. 294-305.

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R. Rajwar and J. R. Goodman. "Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution", in Proc. of 34th Intl. Symp. on Microarchitecture (MICRO), pp. 294-305, Dec. 2001.

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R. Rajwar and J. R. Goodman. Speculative lock elision: Enabling highly concurrent multithreaded execution. In 34 Symposium on Microarchitecture, December 2001.

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Ravi Rajwar and James R. Goodman. Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution. In International Symposium on Microarchitecture(MICRO34), December 2001.

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