L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In M. Franklin, P. Crowley, H. Hadimioglu, and P. Onufryk, editors, Network Processor Design Issues and Practices, Volume 1, chapter 4, pages 55--90. Morgan Kaufmann, October 2002.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....tradeo#s between RISC, superscalar, and multithreaded architectures (as discussed in Section 2.3. 1) In more recent work, a modelling framework is proposed that considers the data flow through the system [CB02] Thiele et al. have proposed a very general performance model for network processors [TCGK02] It takes into account the workload of the system in terms of data tra#c streams, the performance of a processor under di#erent scenarios, and e#ects of the queue system. The model is very general and could provide an interesting approach to network processor design. However, it still has to be ....

Lothar Thiele, Samarjit Chakraborty, Matthias Gries, and Simon Kunzli. Design space exploration of network processor architectures. In Cambridge, MA, February 2002.

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L. Thiele, S. Chakraborty, M. Gries, S. Kunzli, Design space exploration of network processor architectures, in: P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk (Eds.), Network Processor Design: Issues and Practices, Vol. 1, Morgan Kaufmann Publishers, 2002, pp. 55--89.

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L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In Crowley et al. [48], chapter 4, pages 55--90. A preliminary version of this paper appeared in the Proc. 1st Workshop on Network Processors, held in conjunction with the 8th International Symposium on High-Performance Computer Architecture, Cambridge, Massachusetts, 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. In P. Crowley, M. Franklin, H. Hadimioglu, and P. Onufryk, editors, Network Processor Design: Issues and Practices, volume 1, pages 55--89. Morgan Kaufmann Publishers, Oct. 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. In Network Processor Design: Issues and Practices, Volume 1. Morgan Kaufmann Publishers, October 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. In Proc. 1st Workshop on Network Processors, held in conjunction with the 8th International Symposium on High-Performance Computer Architecture, Cambridge, Massachusetts, February 2002.

....analysis, but can also address other system properties in an uniform way such as the memory demand and resource loads. New results. The underlying theory behind our framework (Real Time Calculus) was originally developed in the context of performance evaluation of network processor architectures [11, 12]. However, there were two major shortcomings of the work presented in [11] and [12] i) it was not shown how the framework compares with the theoretical results from the real time systems area, ii) how closely do the performance evaluation results match those obtained by simulation. As already ....

....as the memory demand and resource loads. New results. The underlying theory behind our framework (Real Time Calculus) was originally developed in the context of performance evaluation of network processor architectures [11, 12] However, there were two major shortcomings of the work presented in [11] and [12] i) it was not shown how the framework compares with the theoretical results from the real time systems area, ii) how closely do the performance evaluation results match those obtained by simulation. As already pointed out in [14] without a clarification concerning the above two ....

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L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. In Network Processor Design: Issues and Practices, Volume 1. Morgan Kaufmann Publishers, October 2002.

....styles and their performance. The main goal of this paper is to clearly understand the performance cost trade offs for different network processor topologies and their influence on programmability. In order to avoid time consuming implementation we adapt and deploy an analytical framework [5]. In addition we also implement two differently mapped versions of our IPv4 benchmark [11] on IXP1200 to gain detailed insight into programmability of existing NPU architectures. In the process we also verify the preciseness and usefulness of such an analytical framework compared to a detailed ....

....trace is no longer that large. In contrast analytical models promise a fast evaluation that allows for a larger design space to be explored. In the packet processing domain, 3] presents an approach to explore different cache configurations based on general purpose computing elements. Thiele et al. [5] present a generic approach for modeling applications and architectures in this domain. The framework used in this work is based on [5, 12] The paper is organized as follows: First, we introduce the analytical framework used for performance modeling and exploring trade offs. This follows with a ....

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L. Thiele, S. Chakraborty, M. Gries, S. Knzli, "Design Space Exploration of Network Processor Architectures," Symposium on High Performance Computer Architecture (HPCA8), Cambridge MA, USA, February 2002.

....for a larger design space to be explored. In the packet processing domain, 3] presents an approach to explore different cache configurations based on general purpose computing elements. Lakshamanamurthy et al. 4] present an ad hoc approach limited to the IXP2400 network processor. Thiele et al. [5] present a generic approach for modeling applications and architectures in this domain. This model although specialized to some extent for our domain, provides a natural way to specify different architectural parameters, workloads and application task graphs. To date, no comparison of such ....

....of a multiprocessor system and the packet processing itself. Our chosen, representative network processor scenario thus considers a frequent interleaving of computation and memory accesses using multithreading on a heterogeneous architecture. We have extended the architecture modeling of [5] to enable modeling a network processor such as IXP1200. Indeed, a primary goal of this work is to compare, the implementation of IPv4 forwarding switch application on Intel IXP1200 network processor, with an analytical model of the application mapped to the IXP1200 model. In this process, we hope ....

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L. Thiele, S. Chakraborty, M. Gries, S. Knzli, "Design Space Exploration of Network Processor Architectures," First Workshop on Network Processors at the 8th International Symposium on High Performance Computer Architecture (HPCA8), Cambridge MA, USA, February, 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In M. Franklin, P. Crowley, H. Hadimioglu, and P. Onufryk, editors, Network Processor Design Issues and Practices, Volume 1, chapter 4, pages 55--90. Morgan Kaufmann, October 2002.

No context found.

L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In First Workshop on Network Processors at the 8th International Symposium on High-Performance Computer Architecture (HPCA8), Cambridge MA, USA, Feb. 2002.

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L. Thiele, S. Chakraborty, M. Gries and S. Knzli, "Design space exploration of network processor architectures," Network Processor Design 2002: Design Principles and Practices, Editors: P. Crowley, M. Franklin, H. Hadimioglu, P. Onufryk, Morgan Kaufmann Publishers.

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L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In First Workshop on Network Processors at the 8th International Symposium on High-Performance Computer Architecture (HPCA8), Cambridge MA, USA, Feb. 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design space exploration of network processor architectures. In Proc. of Network Processor Workshop in conjunction with Eighth International Symposium on High Performance Computer Architecture (HPCA-8), pages 30--41, Cambridge, MA, Feb. 2002.

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L. Thiele, S. Chakraborty, M. Gries, and S. K unzli. Design Space Exploration of Network Processor Architectures. In: M.A. Franklin, P. Crowley, H. Hadimioglu, and P.Z. Onufryk (Eds.), Network Processor Design: Issues and Practices Volume, Chapter 4. Morgan Kaufman, 2002.

No context found.

L. Thiele, S. Chakraborty, M. Gries, and S. Kunzli. Design space exploration of network processor architectures. In Network Processor Workshop in conjunction with Eighth International Symposium on High Performance Computer Architecture (HPCA-8), pages 30--41, Cambridge, MA, Feb. 2002.

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