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C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Systems, 2001.

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Physical Design with Multiple On-Chip Voltages - Chunhong Chen Dept   Self-citation (Chen)   (Correct)

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Chen, C., Srivastava A., and Sarrafzadeh M. On gate level power optimization using dual supply voltages. IEEE Trans. on VLSI Systems, 9(5), October 2001, 616-629.


Pushing ASIC Performance in a Power Envelope - Puri, Stok, Cohn, Kung, Pan.. (2003)   (8 citations)  Self-citation (Srivastava)   (Correct)

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C. Chen, A. Srivastava, and M. Sarrafzadeh, On gate level power optimization using dual-supply voltages, IEEE Trans. on VLSI Systems, vol.9, p.616-629, Oct. 2001.


Budget Management with Applications - Chen, Bozorgzadeh, Srivastava.. (2002)   (2 citations)  Self-citation (Chen Srivastava Sarrafzadeh)   (Correct)

....the number of distinct slacks in a given graph, respectively. The space complexity of the algorithm is O(n ) in the worst case. In the above theorem, the value of K strongly depends upon the given graphs and their slack distributions. However, our experience shows K n for most applications [8]. 3.2. Dynamic Characteristics of Budget Management. Since slack distribution is related to given timing constraint T spec , the total slack and maximum effective budget of a given graph G (V, E) are associated with T spec . Let Bm (T ) be the maximum effective budget of G with the timing ....

C. Chen, A Srivastava, and M. Sarrafzadeh, On Gate Level Power Optimization Using Dual Supply Voltages, IEEE Transactions on VLSI Systems, 9(5):616--629, October 2001.


Low-Power FPGA Using - Pre-Defined Dual-Vdd Dual-Vt   (Correct)

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C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Systems, 2001.


Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics - Li, Lin, He, Cong (2004)   (1 citation)  (Correct)

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C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Systems, 2001.


Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics - Li, Lin, He, Cong (2004)   (1 citation)  (Correct)

No context found.

C. Chen, A. Srivastava, and M. Sarrafzadeh, "On gate level power optimization using dual-supply voltages," IEEE Trans. on VLSI Systems, 2001.


Low-Swing Clock Domino Logic Incorporating Dual Supply.. - Seong-Ook Jung..   (Correct)

No context found.

C. Chen, A. Srivastava, and M. Sarrafzadeh. On gate level power optimization using dual-supply voltages. IEEE Trans. VLSI Systems, 9(5):616--629, Oct. 2001.

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