K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proc. Design Automation Conf., 1991, pp. 514--519.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....such as among ASIC s or among blocks on an ASIC. Most such techniques partition at the granularity of arithmetic operations, differing in the partitioning heuristics employed. Clustering heuristics are used in [14] and [15] integer linear programming in [16] and [17] manual partitioning in [18], and iterative improvement heuristics in [19] and [20] Other techniques for hardware partitioning operate at a higher level of granularity, such as in [21] where processes and subroutines are partitioned among ASIC s using clustering, iterative improvement, and manual techniques. Experiments ....

....approach, in which preestimation consists of annotating each behavior and variable with a weight, and then a simple online estimation sums the weights [12] 13] Such an approach is fast, but may be inaccurate since it does not consider hardware sharing. Other research efforts [14] 15] [18], 30] use a design based approach, in which an online estimation roughly synthesizes a design for a given partition, omitting time consuming synthesis tasks such as logic optimization. While more accurate, such estimators may require tens of seconds, which may be too slow for exploration of ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proc. Design Automation Conf., 1991, pp. 514--519.

....points to synthesize RTL designs that satisfy these estimates. In the traditional heterogeneous model of integrated HLS and spatial partitioning, the partitioner invokes a HLS estimator to obtain the area latency of each spatial partition. Several heterogeneous systems, such as SpecSyn [5] Chop [6] and Vulcan I [7] focussed on providing good design estimates while not performing complete HLS. Later, researchers (COBRA ABS [8] Multipar [9] developed a completely homogeneous model, wherein HLS and partitioning are performed in a single step. The COBRA ABS system has a Simulated Annealing ....

K. Kucukcakar, and A. Parker. "CHOP: A constraint-driven system-level partitioner". In Proceedings of the Conference on Design Automation, pages 514--519, 1991.

....the HLS exploration and estimation phase with partitioning. This led to the traditional heterogeneous model, shown in Figure 1(a) where the design area and latency costs of each contemplated partition segment was evaluated by the HLS phase. Several heterogeneous systems, such as SpecSyn [5] Chop [6] and Vulcan I [7] focussed on providing good design estimates while not performing complete HLS. Later, researchers (COBRA ABS [8] Multipar [9] developed a completely homogeneous model, wherein high level synthesis and partitioning are performed in a single step. The COBRA ABS system has a ....

K.Kucukcakar, and A.Parker. "CHOP: A constraint-driven systemlevel partitioner". In Proceedings of the Conference on Design Automation, pages 514--519, 1991.

....The most accurate would be to synthesize a design for the set of functions, but such an approach requires too much time if we wish to examine more than a few possible partitions, as is usually the case. To overcome this limitation, several research efforts incorporate a hardware size estimator [2, 3, 4, 5]. In essence, those estimators roughly synthesize a design for the given functions, while omitting the timeconsuming synthesis tasks such as logic optimization, so they require only a few seconds to obtain a fairly accurate estimate. Such estimators based on a design model have the advantage of ....

....the extremely fast time per move shown. The last two columns demonstrate the increased speed compared with a previous design based estimator [16] That estimator requires roughly 3 seconds for a given partition, which is the same magnitude of time required by several other designbased estimators [2, 3]. Multiplying by the number of moves yields a predicted estimation time; note the unacceptably long times for the large number of moves examined. The last column shows the speedup of our estimator over those previous ones, ranging from 426 to 755; such speedup is obtained while using the same ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....process. After partitioning, structure may be designed separately for each package. The advantages included greatly reduced I O (often 50 ) improved performance, and reduced synthesis runtimes (often by an order of magnitude) Such advantages were predicted by some researchers for many years [5, 6, 7, 8, 9]. In addition, since programs are being partitioned rather than gates, the approach supports hardwaresoftware partitioning, unlike structural partitioning which is for hardware only. Many hardwaresoftware functional partitioning approaches have recently been proposed [10, 11, 12, 13, 14, 15, 16, ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....arithmetic operations and partitioning them among ASICs. In [22] an ILP formulation is presented that selects a set of processors on which to implement a set of performance constrained processes, and to partition the processes among those processors. Some other related works include that in [23], which provides techniques for rapid size and time estimation for a partition of arithmetic operations among ASICs. Research pre23 sented in [1] and [24] overviews the hardware software partitioning problem, including discussions on granularity, estimation, and simulation of interacting hardware ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, 1991.

....functionality among hardware or hardware software components. The need for coarse grained procedural level partitioning was stressed in [2] as well as in [3, 4] Approaches in [5, 6, 7] partition at the finer grained statement level (or statement sequence) Other approaches, such as those in [8, 9, 10, 11, 12, 13], partition at the fine grained arithmetic operation level. Additional research has focused on functional transformation, at a procedural level of granularity in [14, 15] at a loop and statement level in [16] and at an operation level in [17] Details on several of these efforts can be found in ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in DAC, 1991.

....functions are implemented as structure. The existence of functional specifications means that such functional partitioning can now be automated. In fact, several research efforts have addressed such automation, hypothesizing that functional partitioning would excel over structural partitioning [10, 11, 12, 13, 14]. This paper provides empirical results for the hypothesis that: Functionally partitioning a specification results in better satisfaction of hardwarepart size and I O constraints, and often yields better design performance, than achievable through structural partitioning. For example, consider ....

....arithmetic operations. These atomic objects will be assigned to parts during partitioning. Fine granularities yield more partitioning choices, but require longer heuristic runtimes and result in less accurate estimations [16] Many systems partition at the granularity of arithmetic operations [10, 11, 30, 12]. Partitioning heuristics can be classified as either iterative improvement or constructive heuristics. Constructive heuristics start with no initial partition, and build a partition. A common constructive heuristic is clustering, in which objects deemed by a closeness function to be close to ....

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K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....techniques for partitioning among hardware packages. Most e#orts partitioned arithmetic level operations. Aparty [8] partitioned operations among datapath modules using multi stage clustering. Vulcan [14] partitioned operations among packages using iterative improvement heuristics. Chop [15] partitioned operations among packages, focusing on providing a suite of feasible solutions for each package that would satisfy overall constraints. Multipar [16] and Gebotys techniques [17] partitioned operations among packages simultaneous with scheduling and allocation, using integerlinear ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in DAC, pp. 514--519, 1991.

....operations, but with the goal of satisfying packaging constraints and extracting some parallelism. Other arithmetic operation level approaches with the goal of multi chip partitioning combined partitioning with the behavioral synthesis tasks of scheduling and component allocation [18] 19] [20]. Our early work shared the multi chip partitioning goal, but focused at the higher level granularity of procedures rather than arithmetic operations [21] Since then, we have proposed numerous heuristics and estimation models for such partitioning [10] Regardless of whether we perform ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, 1991, pp. 514--519.

....p. 4 Related work There are several research efforts that focus on performing system design tasks. Several efforts have focused on partitioning functionality among a hardware software architecture [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13] for partitioning functionality among hardware modules [14, 15, 16, 17, 18, 19, 20, 21, 22, 23], for partitioning functionality among multiple processors [24] and for transformation during system design [25, 26] Many of these efforts use an intermediate format intended to expose control and data dependencies between fine grained operations, such as the Value Trace [16, 25] the Sequencing ....

.... for transformation during system design [25, 26] Many of these efforts use an intermediate format intended to expose control and data dependencies between fine grained operations, such as the Value Trace [16, 25] the Sequencing Intermediate Format [14] and variations of a control dataflow graph [17, 19]; those formats were originally developed for high level synthesis (see also [27, 28, 29] Those formats may be too fine grained for systemdesign tasks. To our knowledge, SLIF is one of the first published internal formats intended for the system level design tasks. An exception is the ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, 1991.

....[Cam87] Lagnese and Thomas [Lag89] generalized their work by considering multi stage clustering. Gupta and De Micheli [Gup90] proposed both simulated annealing and heuristic approaches for partitioning of programmable and hardwired designs [Gup90] Other notable efforts in partitioning include [Kuc91, Pra91, Vah92, Rao92] 6 of 12 Problems Formulation, Graph Theoretic Abstraction, Complexity, and Optimization Strategy 4.0 Problems Formulation, Graph Theoretic Abstraction, Complexity, and Optimization Strategy In this section, we formulate the problem of throughput optimization. Next, we show how to reformulate ....

K. Kucukcakar, A.C. Parker, "CHOP: A Constraint-Driven System-Level Partitioner", 28th DAC, pp. 514-519, 1991.

....complexity and designer interaction. The case for procedural level granularity during system partitioning has been presented in [4, 5, 6, 7] although those efforts did not address the issue of closeness metrics. Other functional partitioning efforts include operation level approaches in [8, 9, 10, 11], statement sequence level approaches in [12, 13] and state level approaches in [14, 15] Our closeness metrics can be used in conjunction with the procedural, statement sequence, or state level approaches. The paper is organized as follows. In Section 2, we provide a problem definition. In ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....modules, such as among ASICs or among blocks on an ASIC. Most such techniques partition at the granularity of arithmetic operations, differing in the partitioning heuristics employed. Clustering heuristics are used in [14, 15] integer linear programming in [16, 17] manual partitioning in [18], and iterative improvement heuristics in [19, 20] Other techniques for hardware partitioning operate at a higher level of granularity, such as in [21] where processes and subroutines are partitioned among ASICs using clustering, iterative improvement, and manual techniques. Experiments have ....

....use a weight based approach, in which pre estimation consists of annotating each behavior and variable with a weight, and then a simple online estimation sums the weights [12, 13] Such an approach is fast, but may be inaccurate since it doesn t consider hardware sharing. Other research efforts [14, 15, 30, 18] use a design based approach, in which an online estimation roughly synthesizes a design for a given partition, omitting time consuming synthesis tasks such as logic optimization. While more accurate, such estimators may require tens of seconds, which may be too slow for exploration of thousands ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....involves minimizing the number of transfers between partitions. Obviously, this will effect the number of buses. This paper assumes that the system has previously been partitioned. Nevertheless it is important to note that their has been a large amount of research into the partitioning problem [7, 10, 8, 5]. Some research on partitioning considers the quality of the final design. For example, Gupta and De Micheli [6] present an algorithm for partitioning and then use the area and latency of the resulting system as a criterion for evaluating the partition. Similarly [1] presents a partitioning ....

K. Kucukcakar and A. Parker, "CHOP: A Constraint-Driven System-Level Partitioner," Proc. 28th ACM/IEEE Design Automation Conference, 1991, pp. 514-519.

....the reductions in I O (maximum on either part, and total on both parts) obtained when using functional partitioning instead of structural partitioning. Several early functional partitioning approaches focused on partitioning arithmetic level data and control operations among hardware blocks [13, 14, 15, 16, 17], while others have focused on partitioning coarser grained functions (algorithmic level subroutines) 18] More recently, the problem of partitioning among hardware and software blocks has attracted much attention [19, 20, 21, 22, 23, 24, 25, 26] most of this focus uses coarsergrained functions. ....

K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....Work Synthesis for reconfigurable architectures involves synthesis and partitioning. The partitioning can be both temporal and spatial. There has been significant research on spatial partitioning and synthesis, though the issue of temporal partitioning has been largely ignored. Early research [11, 12] in the synthesis domain solved the spatial partitioning problem independently from the scheduling and allocation subproblems. The problem of simultaneous spatial partitioning and synthesis was first formulated as an IP by Gebotys in [1] It produced synthesized designs which were 10 faster than ....

K. Kucukcakar and A. Parker, "CHOP: A Constraint-Driven-System-Level Partitioner", DAC, p514-519, 1991.

....for partitioning among hardware packages. Most e#orts partitioned arithmetic level operations. Aparty [9] partitioned operations among datapath modules or packages using multi stage clustering. Vulcan [15] partitioned operations among packages using iterative improvement heuristics. Chop [16] partitioned operations among packages, focusing on providing a suite of feasible solutions for each package that would satisfy overall constraints. Multipar [17] and Gebotys techniques [18] partitioned operations among packages simultaneous with scheduling and allocation, using integer linear ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....each package s functions are implemented. The existence of functional specifications means that such functional partitioning can now be automated. In fact, several research efforts have addressed such automation, hypothesizing that functional partitioning would excel over structural partitioning [10, 11, 12, 13, 14]. This paper provides empirical results supporting that hypothesis. Intuitively, functional partitioning excels by assigning each function to one part, rather than spreading a function over several parts. Such isolation: 1) reduces I O, 2) prevents the critical path from crossing parts, thus ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....without incurring much higher partition cost. Previous efforts in clustering during functional partitioning include clustering of logic operations [2] arithmetic operations [3, 4] and statements [5] Other related functional partitioning efforts include arithmetic operation level approaches [6, 7, 8, 9, 10], statement sequence level approaches [11, 12] and state level approaches [13, 14] Our work differs from the above works in two ways. First, we investigate various combinations of clustering heuristics with iterative improvement heuristics, rather than just one or the other. Second, we use ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

....[1, 4, 5, 6, 7, 8] as well as hardware hardware partitioning [9, 10, 11, 12] The former techniques focus on maximizing performance while minimizing hardware size, and the latter on satisfying packaging constraints while minimizing communication time. Other techniques assume a manual partitioning [13, 14, 15, 16, 17], but could certainly be extended to use heuristics. The work presented here is intended to greatly improve the ability to make fair comparisons of various heuristics. In particular, we need a well defined model on which to apply partitioning heuristics. A model represents the specification ....

K. Kucukcakar and A. Parker, "CHOP: A constraintdriven system-level partitioner," in Proceedings of the Design Automation Conference, pp. 514--519, 1991.

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K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proc. Design Automation Conf., 1991, pp. 514--519.

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K. Kucukcakar and A. C. Parker, "CHOP: A constraintdriven system-level partitioner," in Proc. Design Automation Conf., pp. 514-519, June 1991.

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K. Kucukcakar and A. Parker, "CHOP: A constraint-driven system-level partitioner," in Proc. DAC, 1991, pp. 514--519.

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K. Kucukcakar and A. C. Parker, "CHOP: A Constraint-Driven System Level Partitioner, " Proceedings of the Design Automation Conference (DAC), pp. 514-519, June 1991.

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