W. Dougherty et al. Instruction subsetting: Trading power for programmability. In Proc. Workshop on System Level Design, 1998. Home/Search Document Details and Download
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Extended Design Reuse Trade-Offs in.. - Vermeulen.. (2000) (Correct)
....Virtex XCV600 FPGA and power has been estimated with Xilinx Virtex Power Estimator 1.5. Between ASICs and general purpose instruction set processors, a large range of ASIP instruction set architectures can be designed, where flexibility and design time are spentto gain performance. W. Dougherty[24]et al. have found a factor 3power increase going from an ASIC to a minimal ASIP for a FIR filter. We made an estimation of a best case power consumption in an ASIP based on the power attribution in a StrongARM [25] lowpower processor and assuming the best case of same datapath and internal memory ....
W.Dougherty, D.Pursley, D.Thomas, "Instruction Subsetting: Trading Power for Programmability," IEEE Wshop on VLSI 1998.
Energy-Efficient Instruction Set Synthesis for.. - Lee, Choi, Dutt (2003) (Correct)
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W. Dougherty et al. Instruction subsetting: Trading power for programmability. In Proc. Workshop on System Level Design, 1998.
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