Dean Kawaguchi and Sarosh Vesuna. Symbol Technologies, Inc. Automates Ssystem-To-Gates Design Flow For Wireless LAN ASIC with COSSAP and Behavioral Compiler. Mountain View, California. Available at http://www.synopsys.com/news/pubs/bctb/sep98/frame_art1.html, September 1998. Home/Search Document Not in Database Summary Related Articles Check |
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Wormhole Detection in Wireless Ad Hoc Networks - Hu, Perrig, Johnson (2002) (6 citations) (Correct)
....representing a rate of 222,000 hashes per second. Repetitive, simple functions like hashes can also be efficiently implemented in hardware; Helion Technology [17] claims a 20k gate ASIC core design (a third the complexity of Bluetooth [3] and less than a third the complexity of IEEE 802.11 [22]) capable of more than 1.9 million hashes per second and a Xilinx FPGA design using 1650 LUTs capable of 1 million hashes per second. In terms of memory consumption, existing handheld devices, such as the iPaq 3870, come equipped with 32 MB of Flash and 64 MB of RAM. Modern notebooks can generally ....
Dean Kawaguchi and Sarosh Vesuna. Symbol Technologies, Inc. Automates Ssystem-To-Gates Design Flow For Wireless LAN ASIC with COSSAP and Behavioral Compiler. Mountain View, California. Available at http://www.synopsys.com/news/pubs/bctb/sep98/frame_art1.html, September 1998.
Packet Leashes: A Defense against - Wormhole Attacks In (Correct)
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Dean Kawaguchi and Sarosh Vesuna. Symbol Technologies, Inc. Automates Ssystem-To-Gates Design Flow For Wireless LAN ASIC with COSSAP and Behavioral Compiler. Mountain View, California. Available at http://www.synopsys.com/news/pubs/bctb/sep98/frame_art1.html, September 1998.
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