F. Najm, I. Hajj, and P. Yang, "Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits," IEEE Transactions on Computer-Aided Design, pp. 439-450, April 1990. Home/Search Document Details and Download
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Accurate And Fast Power Estimation Of Large.. - Theoharis.. (1999) (Correct)
....are used in order to evaluate the transitions of any circuit node. The above methods can be classified according to assumed gate delay model in the following categories i) the zero delay methods [3] 6] where only the functional transitions are considered and the ii) real gate delay methods [7] [9] where both the functional and spurious transitions are taken into account. Hence, real gate delay model is needed for accurate power estimation. In addition temporal correlation, input pattem dependencies and spatial (structural) dependencies have to be considered to estimate accurate the ....
....functional and spurious transitions are taken into account. Hence, real gate delay model is needed for accurate power estimation. In addition temporal correlation, input pattem dependencies and spatial (structural) dependencies have to be considered to estimate accurate the power dissipation. In [7] the concept of the probability waveforms to estimate the average power dissipation of a combinational circuit was introduced. Given the probability waveforms of the primary inputs, a propagation algorithm of these waveforms through the circuit to evaluate the corresponding waveforms of the ....
F. Najm, R. Burch, P.Yang and I. Hajj "Probabilistic Simulation for Reliability Analysis of CMOS VLSicircuits," in IEEE Trans. on CAD, 9 (4) pp. 439-450, Apr. 1990.
Design Technologies for Low Power VLSI - Pedram (1997) (2 citations) (Correct)
....activity of x which includes the contribution of hazards and glitches, that is: 5) Given such waveforms at the circuit inputs and with some convenient partitioning of the circuit, the authors examine every sub circuit and derive the corresponding waveforms at the internal circuit nodes. In [45], an efficient probabilistic simulation technique is described that propagates transition waveforms at the circuit primary inputs up in the circuit and thus estimates the total power consumption (ignoring signal correlations due to the reconvergent fanout nodes) A tagged probabilistic simulation ....
F. N. Najm, R. Burch, P. Yang, and I. Hajj. " Probabilistic simulation for reliability analysis of CMOS VLSI circuits. " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
Average Power in Digital CMOS Circuits using Least.. - Murugavel.. (2001) (Correct)
....the signal probabilities provided by the user, are propagated through the circuit and the power at each node is computed based on the temporal dependence assumption. The CREST model [4] makes use of probability waveforms instead of discrete probability values. An efficient algorithm is proposed in [5] where the transition densities are propagated through the circuit and the power is calculated at each node. Here, transition density is the average number of transitions per second at a given node. Binary Decision Diagrams (BDD) are used in [5] for power estimation. Non Simulative Najm Average ....
....values. An efficient algorithm is proposed in [5] where the transition densities are propagated through the circuit and the power is calculated at each node. Here, transition density is the average number of transitions per second at a given node. Binary Decision Diagrams (BDD) are used in [5] for power estimation. Non Simulative Najm Average Power Estimation [1] Burch Cirit [8] Najm [18] Chih Shun et al. [11] Yuan et al. Yuan et al. Gupta et al. Marculescu et al. Xakellis et al. [12] 21] 16] 17] Burch et al. Najm et al. Najm et al. Najm Najm [9] 20] 13] 22] Ghosh ....
R Burch, F Najm, P Yang, and I Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits ", IEEE Trans. on Computer-Aided Design of Integrated Circuits, Vol.9, No.7, Jul 1990.
Computation of Bus Current Variance for Reliability.. - Najm, Hajj, Yang (1989) Self-citation (Najm) (Correct)
....ESTimator) has proven to be very effective both in terms of accuracy and speed. We focus on the power and ground busses, and derive currents for them to be used for MTF estimation. In the interest of clarity, we will review some of the basic concepts behind this approach. The reader is referred to [7] for a more detailed description. The argument presented in [7] is that the correct current waveform to be used for MTF estimation is one that combines the effects of all possible input waveforms. By considering the set of logical waveforms allowed at the circuit inputs as a probability space ....
....and speed. We focus on the power and ground busses, and derive currents for them to be used for MTF estimation. In the interest of clarity, we will review some of the basic concepts behind this approach. The reader is referred to [7] for a more detailed description. The argument presented in [7] is that the correct current waveform to be used for MTF estimation is one that combines the effects of all possible input waveforms. By considering the set of logical waveforms allowed at the circuit inputs as a probability space [5] the current in any branch of the bus becomes a stochastic ....
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F. Najm, "Probabilistic simulation for reliability analysis of VLSI circuits," Ph.D. thesis, Dept. of Electrical and Computer Engineering, University of Illinois at UrbanaChampaign, June 1989. 10 Figure Captions
Transition Density, A New Measure of Activity in Digital Circuits - Najm (1992) (78 citations) Self-citation (Najm) (Correct)
....the independence property. This problem is central to any circuit analysis based on a statistical representation of signals, and can usually be taken care of by using heuristics that trade off accuracy for speed [5 9] Based on our previous experience with the propagation of probability waveforms [12], we have found that, if the modules are large enough so that tightly coupled nodes (such as in latches or small cells) are kept inside the same module, then the coupling outside the modules is sufficiently low to justify an independence assumption. While this does take into account the ....
F. N. Najm, R. Burch, P. Yang, and I. N. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design, pp. 439--450, April 1990.
Transition Density, A Stochastic Measure of Activity in.. - Farid Najm Semiconductor (1991) (34 citations) Self-citation (Najm) (Correct)
....destroy the independence property. This problem is central to any circuit analysis based on a statistical representation of signals, and can usually be taken care of by using heuristics that trade off accuracy for speed [4 8] Based on our experience with the propagation of probability waveforms [11], we have found that, if the modules are large enough so that tightly coupled nodes (such as in latches or small cells) are kept inside the same module, then the coupling outside the modules is sufficiently low to justify an independence assumption. Of course, one can model the whole circuit as a ....
F. N. Najm, R. Burch, P. Yang, and I. N. Hajj, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Tras. Computer- Aided Design, pp. 439-450, April 1990.
Low Power Architectural Design Methodologies - Landman (1994) (22 citations) (Correct)
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F. Najm, I. Hajj, and P. Yang, "Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits," IEEE Transactions on Computer-Aided Design, pp. 439-450, April 1990.
Probabilistic Modeling of Dependencies During Switching.. - Radu Marculescu Diana (1998) (1 citation) (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj, `Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits', in IEEE Trans. on CAD, vol. CAD-9, pp. 439-450, April 1990.
Power Simulation and Estimation in VLSI Circuits - Pedram (1999) (2 citations) (Correct)
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F. Najm, R. Burch, P. Yang, I. Hajj, "Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits," IEEE Transactions on CAD, Vol. 9, No. 4, pp. 439-450, 1990.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) (Correct)
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F. Najm, R. Burch, P. Yang, I. Hajj, "Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits," IEEE Transactions on CAD, Vol. 9, No. 4, pp. 439-450, 1990.
Revision of Manuscript 42: - Gate-Level Power Estimation (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. N. Hajj. Probabilistic simulation for reliability analysis of cmos circuits. ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
Power Estimation and Optimization at the Logic - Level Massoud Pedram (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990. 26
Improving the Efficiency of Monte Carlo Power Estimation - Chih-Shun Ding Cheng-Ta (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. ieee Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
High-Level Power Modeling, Estimation, and Optimization - Macii, Pedram, Somenzi (1997) (22 citations) (Correct)
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F. Najm, R. Burch, P. Yang, I. Hajj, "Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits," IEEE Trans. on CAD, Vol. 9, No. 4, pp. 439-450, 1990.
Low Power CAD: Trends and Challenges - Massoud Pedram Department (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
Power Minimization in IC Design: Principles and Applications - Pedram (1996) (72 citations) (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj. " Probabilistic simulation for reliability analysis of CMOS VLSI circuits. " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
CAD for Low Power: Status and Promising Directions - Pedram (1995) (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic simulation for reliability analysis of CMOS VLSI circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
Logic Level Power Estimation Considering.. - Marculescu.. (1994) (8 citations) (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj, `Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits', in IEEE Trans. on CAD, vol. CAD-9, April 1990
Switching Activity Estimation Based on Conditional.. - Marculescu, Marculescu.. (1995) (Correct)
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F. N. Najm, R. Burch, P. Yang, and I. Hajj, `Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits', in IEEE Trans. on CAD, vol. CAD-9, April 1990
Probabilistic Modeling of Dependencies During.. - Marculescu.. (1998) (1 citation) (Correct)
No context found.
F. N. Najm, R. Burch, P. Yang, and I. Hajj, `Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits', in IEEE Trans. on CAD, vol. CAD-9, pp. 439-450, April 1990.
Power Minimization in IC Design: Principles and Applications - Pedram (1996) (72 citations) (Correct)
No context found.
F. N. Najm, R. Burch, P. Yang, and I. Hajj. " Probabilistic simulation for reliability analysis of CMOS VLSI circuits. " IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(4):439--450, April 1990.
Switching Activity Estimation using Limited Depth Reconvergent .. - Jos Costa Jos (1997) (14 citations) (Correct)
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F. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits. IEEE Transactions on Computer-Aided Design, 9(4):439--450, 1990.
A Computer-Aided Design Methodology for Low Power Sequential.. - Monteiro (1996) (Correct)
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F. Najm, R. Burch, P. Yang, and I. Hajj. Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits. IEEE Transactions on Computer-Aided Design, 9(4):439--450, April 1990.
Optimization of Custom MOS Circuits by Transistor Sizing - Andrew Conn Paula (1996) (3 citations) (Correct)
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F. Najm, "Probabilistic simulation for reliability analysis of CMOS VLSI circuits," IEEE Transactions on Computer-Aided Design of ICs and Systems, pp. 439-450, volume CAD-9, April 1990.
A VHDL-Based Approach for Power Estimation of Embedded.. - Fornaciari, Gubian.. (Correct)
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F.N. Najm, R. Burch, P. Yang and I.N. Hajj, Probabilistic Simulation for Reliability Analysis of CMOS VLSI Circuits, IEEE Trans. on Computer-Aided Design, 9(4) (
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